The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
The problem of increasing the coefficient of technical readiness of memory module, the value of which increases with decreasing of control system recovery time in case of failure of its constituent units, is solved. The proposed structure of the memory module with built-in self-test and restore functionality that will allow auto-replacing bits of data of the main memory cell array, in which there...
In modern processes, conventional defect density and variability related yield losses are a major concern for the aggressive memory designs in integrated circuits. Synergistic action for memory repair at the circuit and architectural level is essential to maintain the yields and profitability of past technology nodes. In this paper, we propose a scalable memory repair architecture that utilizes a...
In this paper, BISR (built-in self-repair) techniques for heterogeneous multiple memory cores with divided redundancy mechanism are proposed. Redundant memories are partitioned into row blocks and column blocks and shared among all memory cores in the same memory group. Therefore, unlike the traditional redundancy mechanism, a row (column) block is used as the basic replacement element. Based on the...
Future technologies, with ever shrinking devices and higher densities, bring along higher defect rates and lower yield. Memory chips, which are among the densest circuits used in digital systems, are greatly impacted by the increasing defect rates, which make yield fall and production costs rise sharply. In this paper, a new approach for designing memory chips to be manufactured using future technologies...
Software-based self-test (SBST) is increasingly used for testing processor cores embedded in SoCs, mainly because it allows at-speed, low-cost testing, while requiring limited (if any) hardware modifications to the original design. However, the method requires effective techniques for generating suitable test programs and for monitoring the results. In the case of processor core testing, a particularly...
In this paper a BISR architecture for embedded memories is presented. The proposed scheme utilises a multiple bank cache-like memory for repairs. Statistical analysis is used for minimisation of the total resources required to achieve a very high fault coverage. Simulation results show that the proposed BISR scheme is characterised by high efficiency and low area overhead, even for high defect densities...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.