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Network Functions Virtualization (NFV) is a new network paradigm that has been strongly promoted from both scientific community and telecom industry, where network functions (NFs) such as firewalls, load balancers, gateways among others, are virtualized, isolated from middleboxes and housed on one or more industry standard computing nodes. One of the main challenges for service providers when they...
Datacenters should provide bandwidth guarantees to tenants for performance predictability. Ideally, this process should attain three important characteristics: work conservation, fairness, and simplicity. The first one indicates that tenants can utilize unused bandwidths effectively without harming the bandwidth guarantee. The second one means that tenants share the unused bandwidth following a certain...
Recurrent Neural Networks (RNNs) have the ability to retain memory and learn from data sequences, which are fundamental for real-time applications. RNN computations offer limited data reuse, which leads to high data traffic. This translates into high off-chip memory bandwidth or large internal storage requirement to achieve high performance. Exploiting parallelism in RNN computations are bounded by...
Optical Character Recognition is conversion of printed or handwritten text images into machine-encoded text. It is a building block of many processes such as machine translation, text-to-speech conversion and text mining. Bidirectional Long Short-Term Memory Neural Networks have shown a superior performance in character recognition with respect to other types of neural networks. In this paper, to...
The applications of speech interfaces, commonly used for search and personal assistants, are diversifying to include wearables, appliances, and robots. Hardware-accelerated automatic speech recognition (ASR) is needed for scenarios that are constrained by power, system complexity, or latency. Furthermore, a wakeup mechanism, such as voice activity detection (VAD), is needed to power gate the ASR and...
The move from a purely remotely piloted aerial system (RPAS) via air vehicles using automated systems up to a fully autonomous platform is a way that is being followed today. Using automatic take-off and/or landing (ATOL) or waypoint flying, the path towards more complex technologies for RPAS control is clear. Inserting such new technologies into an aerial platform requires extensive testing from...
The paper discusses step-by-step practical flow involved in applying dynamic bandwidth management (DBM) to large industrial system-on-chip (SoC) designs deploying embedded test data compression.
Previous approaches for utilizing automatic test equipment (ATE) vector repeat are based on identifying runs of repeated scan data and directly generating that data using ATE vector repeat. Each run requires a separate vector repeat instruction, so the amount of compression is limited by the amount of ATE instruction memory available and the length of the runs (which typically will be much shorter...
With the advent of cloud computing, encrypting remote program execution becomes plausible. Homomorphic encryption scheme is a potentially promising to realize that. However, it is not practically utilized due to its extremely slow execution speed. The scheme generally requires manipulating arbitrary large operand sizes, reaching out to billions of bits. This paper focuses on multiplication, as it...
Ethernet passive optical network (EPON) is becoming more popular since the users demand more bandwidth each day. A lot of simulation studies have been done in order to study the upstream EPON transmission, but they are less accurate due to assumed parameters and it does not take into account the physical parameters and the non-linear effects of the optical components. Therefore, this paper presents...
Exclusive last-level caches (LLCs) reduce memory accesses by effectively utilizing cache capacity. However, they require excessive on-chip bandwidth to support frequent insertions of cache lines on eviction from upper-level caches. Non-inclusive caches, on the other hand, have the advantage of using the on-chip bandwidth more effectively but suffer from a higher miss rate. Traditionally, the decision...
The use of virtualization in HPC clusters can provide rich software environments, application isolation and efficient workload management mechanisms, but system-level virtualization introduces a software layer on the computing nodes that reduces performance and inhibits the direct use of hardware devices. We present an unobtrusive user-level platform to execute virtual machines inside batch jobs that...
Based on the arbiter template developed in, we presented an efficient, modular, and scalable decentralized parallel design of a new multi-facet arbiter. Moreover, with this modular and reusable hardware design, we have implemented a parametric arbiter generator that automatically generates various multi-facet arbiters. With the decentralized parallel design and the generator, not only a fastest and...
Nowadays, the desire to embed more applications in systems as small as smart cards or sensors is growing. However, physical limitations of these systems, like very small main memory, and their cost of production make this very difficult to achieve. One solution is to execute code from a secondary memory, cheaper, denser, but slower, such as NAND Flash. Solutions based on Demand-Paging and using a...
Three requirements for leased-line service in a packet-transport system are determined such as service availability of 99.999%, bandwidth guarantee of 100%, and latency of 10 ms via 20 nodes. To meet these requirements, network architecture is proposed which includes the separation of control function and data-transmission function and shaping per flow at the entrance of a network. Nodes and gateways...
Experimental validation and testing of solutions designed for heterogeneous environment is a challenging issue. Wrekavoc is a tool for performing such validation. It runs unmodified applications on emulated multisite heterogeneous platforms. Therefore it downgrades the performance of the nodes (CPU and memory) and the interconnection network in a prescribed way. We report on new strategies to improve...
The session Initiation Protocol (SIP) is a widely used application-layer control protocol. The processing load of the SIP protocol is reportedly seen as one of the potential problems which may limit the range of its application although it has a number of advantages. Many research efforts have been made and have come up with various compression algorithms to reduce the packet size in order not to...
We analyze circuits for kernels from popular quantum computing applications, characterizing the hardware resources necessary to take ancilla preparation off the critical path. The result is a chip entirely dominated by ancilla generation circuits. To address this issue, we introduce optimized ancilla factories and analyze theirstructure and physical layout for ion trap technology. We introduce a new...
In this paper, we present the dedicated hardware H.264/AVC video encoder with reducing memory access scheme. This engine performs 30 frame/sec with D1(720x480) resolution at 40 MHz. It has dedicated hardware architecture, memory reducing scheme, double buffering structure to decrease memory bus bandwidth and early decision mode for fast estimation at motion estimation. It supports to H.264/AVC base...
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