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The iterative property of inverse butterfly permutation network makes it possible to implement shift operation with simple routing algorithm, which has high application value in cryptography, digital image processing and other fields. Based on the inverse butterfly network, this paper proposes a subword shift unit, which integrates the operations of subword rotation shift, subword logical shift and...
An ultra-light-weight PRINCE cryptographic processor is developed. A fully-unrolled differential-logic architecture saves delay, energy, and area (i.e. hardware weight) of XOR as a dominant cipher component. An S-box is composed only by four kinds of compact composite gates and a replica-delay-based transition-edge aligner prevents glitches accumulated in the long unrolled combinational-logic data...
A low-end embedded platform for Internet of Things (IoT) often suffers from a critical trade-off dilemma between security enhancement and computation overhead. We propose PUFSec, a new device fingerprint-based security architecture for IoT devices. By leveraging intrinsic hardware characteristics, we aim to design a computationally lightweight security software system architecture so that complex...
Hardening cryptographic algorithms against sidechannel attacks is a complex but crucial task in today's hardware implementations. One of the most promising countermeasures is Boolean Masking. Designers spend much effort to optimise and customise their masking schemes, but many proposed masked implementations were eventually broken, because they are somehow flawed - not necessarily restricted to a...
Differential Power Analysis (DPA) attack is considered to be a main threat while designing cryptographic processors. In cryptographic algorithms like DES and AES, S-Box is used to indeterminate the relationship between the keys and the cipher texts. However, S-box is prone to DPA attack due to its high power consumption. In this paper, we are implementing an energy-efficient 8-bit S-Box circuit using...
The detection of malicious hardware logic (hardware Trojan) requires test patterns that succeed in exciting the malicious logic part. Testing of all possible input patterns is often prohibitively expensive. As an alternative, we explored previously the applicability of the combinatorial testing principles. In this paper, we turn our focus on the efficiency of this approach for triggering the hidden...
We present GarbledCPU, the first framework that realizes a hardware-based general purpose sequential processor for secure computation. Our MIPS-based implementation enables development of applications (functions) in a high-level language while performing secure function evaluation (SFE) using Yao's garbled circuit protocol in hardware. GarbledCPU provides three degrees of freedom for SFE which allow...
The goal of t-private circuits is to protect information processed by the circuit. This work presents the first practical power analysis evaluation of t-private logic style for FPGAs. Following the synthesis technique introduced at HOST 2012, a t-private S-box of the Present block cipher is synthesized and analyzed with respect to side channel leakage. The analysis is performed on simulated power...
RFID is one of the most promising identification schemes in the field of ubiquitous computing. Non line of sight capability makes RFID systems more protuberant than its other alternative systems. RFID systems incorporate wireless medium, so there are some associated security threats and apprehensions to system from malicious adversaries. In order to make the system more reliable and secure, numerous...
The electrical engineering approach to cache coherence is defined not only by the study of IPv7, but also by the natural need for A search 12. In fact, few cyberneticists would disagree with the valuation of write-back caches. Grafter, our new algorithm for cacheable configurations, is the solution to all of these problems.
This paper presents a low power custom hardware implementation of Rijndael S-Box for Advanced Encryption Standard (AES). This custom hardware was designed by using combinational logic unlike the previous works which rely on look-up tables and memory to implement the S-Box. The minimization of power consumption is implemented by optimizing the architecture of the composite field S-Box together with...
This paper presents differences and similarities between experimental and simulated differential power analysis (DPA) based security attacks. DPA attacks are known for many years and experimental attacks have been performed on a large number of hardware and/or software implementations of various cryptographic algorithms (RSA, AES, etc.). Vulnerabilities are mostly discovered after the product has...
Cryptography algorithms are ranked by their speed in encrypting/decrypting data and their robustness to withstand attacks. Real-time processing of data encryption/decryption is essential in network based applications to keep pace with the input data inhalation rate. The encryption/decryption steps are computationally intensive and exhibit high degree of parallelism. Field programmable gate arrays...
We investigate our previously proposed charge sharing symmetric adiabatic logic, which was designed to thwart differential power analysis (DPA) attack. The ability of the logic to withstand DPA attacks is analyzed from the variations in the transitional power consumption of individual logics and in the bit-parallel cellular multiplier over GF(2m). Then, we compare the results with those of the previous...
The intension of this work is to design ASIC (Application Specific Integrated Circuit) for LFSRs (Linear feedback shift register) used in cryptography systems.(Stream ciphering). Presently FPGAs (Field Programmable Gate Array) and Processors are used for this purpose which have speed limitations. Since FPGAs have general structure and implementing LFSRs in FPGAs are unable to achieve the required...
In this paper, we show how Trusted Platform Modules (TPMs), standard security hardware devices, can be used with minor modification to efficiently support Secure Function Evaluation (SFE), a fundamental and extremely powerful cryptographic operation. Prior research by others has shown how SFE can benefit from using security hardware, but prior work has used either custom hardware tokens or powerful...
Test access mechanisms are critical components in digital systems. They affect not only production and operational economics, but also system security. We propose a security enhancement for system-on-chip (SoC) test access that addresses the threat posed by untrustworthy cores. The scheme maintains the economy of shared wiring (bus or daisy-chain) while achieving most of the security benefits of star-topology...
In this paper, efficient hardware of one of the most popular encryption algorithms, the Advanced Encryption Standard (AES), is presented. A modified sub-pipelined structure is proposed targeting high speed and low power-delay product of the compact AES design with on-the-fly key expansion unit. By adding 25.8% in hardware complexity to the existing ASIC designs, the throughput is increased more than...
Cryptography is one of the fundamental components for secure communication of data and authentication. However, cryptographic algorithms impose tremendous processing power demands that can be a bottleneck in high-speed networks. The implementation of a cryptographic algorithm must achieve high processing rate to fully utilize the available network bandwidth. To follow the variety and the rapid changes...
Advanced Encryption Standard (AES) is one of the most common symmetric encryption algorithms. The hardware complexity in AES is dominated by AES substitution box (S-box) which is considered as one of the most complicated and costly part of the system because it is the only non-linear structure. The proposed work employs a combinational logic design of S-Box implemented in Virtex II FPGA chip. The...
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