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In this paper an all-digital frequency locked loop — which is composed of a digitally controlled oscillator, a counter and a latch (with the scope of frequency detection) and an accumulator in the control loop — is modeled in the z-domain considering two significant error sources that occur in its structure: the finite resolution of the digital signals and the inaccuracy of the frequency detection...
For a grid-connected Voltage-Source Converter (VSC), dynamics of the grid synchronization plays an important role in affecting the converter performances and stability. Due to its significance, this paper gives a comparative analysis about some basic grid synchronization schemes, through viewpoint of dynamic performances, which appeared as the impacts of voltage perturbation on the estimated angle...
In this paper a current-limiting droop control of grid-tied inverters that introduces virtual inertia and operates without a phase locked loop unit is proposed. The proposed controller inherits a self-synchronization function and can guarantee tight bounds for the inverter frequency. In addition, using nonlinear Lyapunov theory, it is analytically proven that the inverter current never violates a...
One of the main revenue streams of the power system industries is provide a stable frequency all the time. Energy storage systems are well suited for the purpose because of their bidirectional capabilities. Recently converter based energy storage system has been gaining interests for providing frequency response replacing traditional generator based solutions due to the speed of the power electronic...
With more renewable resources integrated to the grid, energy storage is expected to rise to the challenge of the grid caused by the characteristics of the intermittent renewable sources. This paper presents an innovative battery energy storage system (BESS) combined with the decoupled PQ control and adaptive capacity-based droop control for both grid-connected operation and stand-alone operation....
Design of a stable Phase Locked Loop (PLL) working in MHz frequency range is proposed. Focus of this work is to achieve a symmetric design, where rise and fall time are equal for low operating frequencies. All the blocks of PLL i.e Phase Frequency Detector (PFD), Charge Pump and Loop Filter (CPLF), Voltage Controlled Oscillator (VCO) and Frequency Divider (FD) are carefully designed and integrated...
Phase-locked loops (PLLs) are commonly used for the synchronization of grid connected power converters. However, the standard PLL structures are not able to reject grid disturbances such as voltage harmonics, unbalances or DC components in the measured voltage. Since the response of the power converters depends on the grid phase tracking, it is necessary to ensure an accurate synchronization even...
A new implementation of the recently proposed fixed-frequency two-sample (2S) quadrature generation subsystem (QSG) digital Phase Locked Loop PLL, applicable to single-phase Power Factor Correction (PFC), is proposed. Its characteristics are high accuracy and low computational burden. The proposed PLL includes a frequency feedback loop to improve the synchronization under line frequency variations...
The problem of improving the phase-locked loop (PLL) high-speed performance in the mode of synchronism recovery, interrupted by a large unpredictable disturbance is considered. It is suggested to carry out the control of output signals of digital frequency dividers in addition to frequency control. It is demonstrated experimentally that the result of such a control is the rapid recovery of the synchronism...
This paper presents an adaptive clocking control circuit to mitigate the processor performance degradation due to on-die supply voltage droops. The circuit utilizes multi-path TDC to reduce quantization errors and thermometer code-based data processing to eliminate latches, which shortens frequency modulation latency. This results in faster frequency/supply tracking. A test chip including the adaptive...
This paper presents an adaptive clocking control circuit to mitigate the processor performance degradation due to on-die supply voltage droops. The circuit utilizes multi-path TDC to reduce quantization errors and thermometer code-based data processing to eliminate latches, which shortens frequency modulation latency. This results in faster frequency/supply tracking. A test chip including the adaptive...
A digital frequency synthesizer is proposed to support the burst-frequency switch for a motion controller. The proposed digital frequency synthesizer consists of a phase-locked loop (PLL) generating a 63-phase clock with a frequency of 128 MHz and a programmable open-loop fractional divider. It generates an output clock with a frequency resolution of 0.1% over a frequency range from 0.5 kHz to 32...
In this paper, we propose the model of a network consisting of All-Digital Phase-Locked Loop Network in application to Clock-Generating Systems. The method is based on a solution of a system of non-linear finite-difference stochastic equations and allows us to perform high speed simulations of a distributed Clock Network on arbitrary topology. The result of our analysis show a good agreement with...
This paper introduces an advanced phase-locked-loop (PLL) control structure for an electromagnetically actuated fast steering mirror (FSM). It enables a performance improvement when tracking Lissajous trajectories on a modified FSM. The dynamics of the FSM are inserted into the phase control loop of the PLL control structure, such that frequency and phase of the output and the reference signal are...
Multiphase PLLs suffer from phase errors in the generated phases of the oscillator. These errors perturbate the oscillator's control voltage and fractional spurs are generated along with the intended carrier frequency. In this brief, a simple multiphase fractional PLL is described and a model of the fractional spurs due to the phase errors is presented. Simulation results of generated spurs of the...
This paper presents AC microgrid operation in grid connected and islanded mode. Accurate detection of distributed energy resources (DERs) islanding from utility grid is necessary to initiate any control action within the microgrid. In order to detect islanding occurrence, an adaptive synchronous reference frame phase locked loop (ASRF-PLL) has been utilized in this paper. This modified PLL provides...
Fuel-cell, PV, wind power etc. alternative energy sources are gaining popularity now-a-days because they are reusable energy sources. To feed the alternating power to utility, a grid-tied inverter is necessary as an interfacing equipment. There are many strategies to control the grid tied inverters. In this paper, to control the output current of the grid tied inverters, unified constant-frequency...
This paper proposes a direct power control (DPC) strategy for the grid-connected voltage source inverter (VSI) without phase-locked loop (PLL) under harmonically distorted voltage conditions. A virtual angular is employed instead of the voltage vector angular acquired by the PLL. The second-order vector integrator (SOVI) is integrated with the DPC to implement two different control targets of smooth...
In the micro-grid, renewable energy is used as power generations and source voltage fluctuated. So we proposed to use Matrix Converters (MCs) which have voltage control ability instead of transformers to supply a certain amount of power for the consumer sides [1]. To suppress the fluctuation of the amplitude of the source voltage, we had proposed a load voltage control method for the MCs [2] [3]....
This paper deals with simple design and control of single-phase PWM rectifier which plays an important task in new commercial and low cost uninterruptible power supplies (UPSs). Firstly, a simple and fast single-phase phase locked loop (PLL) is proposed which is one of the main parts of control system. Besides, an efficient design of passive elements of rectifier is proposed to reduce size and cost...
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