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The impact of strain-induced oxide trap charge on the performance and reliability of fully silicided (FUSI)-metal-gate silicon-on-insulator (SOI) MOSFETs is investigated. High strain from a contact etch stop layer (CESL) in FUSI-gate transistors increases channel mobility and drain current driving. A CESL nMOSFET with a thick SOI demonstrates increased hot-electron degradation than its thin SOI counterpart...
Wire bonding is still a very common method for connecting the pads on a chip to the package. During the ultrasonic wire bonding process, several failures such as ball neck failure, missing ball, bond metal peeling or crack etc., may be generated. Of those failures, bond pad peeling or crack is a phenomenon detected after bonding process and is identified as a critical reliability problem and is known...
A fast and simple electrical method is developed to characterize the etch bias and post-patterned ILD breakdown strength of back-end-of-line (BEOL) interconnects, as well as the middle-of-line (MOL) contact/poly module. The method provides a timely and valuable monitoring mechanism for assessing lithography, etch, thin-film quality and process reliability windows.
Polarities of plasma charging damage in n- and p-channel MOSFETs with Hf-based high-k gate stack (HfAlOx/SiO2) were studied for two different plasma sources (Ar-and Cl-based gas mixtures), and found to depend on plasma conditions, in contrast to those with conventional SiO2. For Ar-plasma, which was confirmed to induce a larger charging damage, both n- and p-ch MOSFETs with high-k gate stacks suffer...
ESD protection capability of SOI CMOS output buffers has been studied with human body model (HBM) stresses of both positive and negative polarity. Experimental results show that the ESD discharge current is absorbed by the NMOSFET alone. Unlike bulk technologies where the bi-directional ESD failure voltages are limited by positive polarity stresses, SOI circuits display a more serious reliability...
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