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A method for fabrication of VeSFETs, three-dimensional fin-type MOS transistors is presented. The VeSTIC process was developed and experimentally implemented in ITE. The test devics were manufactured, and their electrical characteristics were measured. Methods for extraction of a set of the VeSFET physical parameters are proposed based on the device compact model. The flat-band voltage, mobility and...
In this paper, we propose a capacitor-less 1T-DRAM structure with the pass-way trench for improving the Retention Time (RT). We have improved the device fabrication process to form the pass-way trench of the structure which combines the Vertical Channel and the Gate-All-Around structure (PTVCT). The memory operation and its attractive performance in terms of programming window, retention time, and...
A new horizontal current bipolar transistor (HCBT) is developed and integrated with a commercial 0.18 mum CMOS technology resulting in a very low-cost BiCMOS technology suitable for wireless applications. The number of fabrication steps is significantly reduced in comparison to conventional vertical-current bipolar transistors. The optimum HCBT performance can be achieved by 3 additional masks to...
Polarities of plasma charging damage in n- and p-channel MOSFETs with Hf-based high-k gate stack (HfAlOx/SiO2) were studied for two different plasma sources (Ar-and Cl-based gas mixtures), and found to depend on plasma conditions, in contrast to those with conventional SiO2. For Ar-plasma, which was confirmed to induce a larger charging damage, both n- and p-ch MOSFETs with high-k gate stacks suffer...
The power consumption and the matching will be the principal issues at the 32 nm node and below. In this context, Ultra-Thin Body devices are extensively studied for the end-of-roadmap CMOS. In this paper we present the SON technology, leading to the simple fabrication of sustained mono-Si nano-membranes over an empty tunnel, and discuss on the application of this process to build-up electronic devices...
Plasma-exposed Si surface related to Si recess in source/drain region was investigated in detail for various superposed bias configurations with frequencies of 13.56 MHz and 400 kHz. Two different bias powers were utilized by an inductively coupled plasma reactor (ICP). The surface layer (SL) and the interfacial layer between the SL and Si substrate (IL) were analyzed by spectroscopic ellipsometry...
We have observed new charge trapping phenomena in sub-80-nm DRAM recessed- channel-array-transistor (RCAT) after Fowler-Nordheim (FN) stress. Gate stack process strongly affected the charge trapping and the trap generating in oxide bulk and interface of RCAT. According to the trapped charges and/or the generated traps after FN stress, the data retention time and writing capabilities of DRAM were dramatically...
The integration of vertical natural capacitors (VNCap) into existing backend-of-line (BEOL) stacks is an important aspect to enable radio-frequency and mixed signal features without extra mask costs. From manufacturing and reliability point of view these devices can be rather challenging since they may contain millions of vias and meters of metal interconnects. In this paper we will discuss the robustness...
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