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In operation of series-connected IGBTs a voltage balancing is necessary, during short circuits it is even more important. Within this paper the behavior of series-connected IGBTs and diodes during the short-circuit type 2 and 3 is analyzed. The dv/dt during the short circuit is determined by one of two equivalent circuit capacitances. One is the plasma capacitance and the second one is the Miller...
In this paper, microwave transmission properties of suspended single-walled carbon nanotubes (SWCNTs) have been investigated up to 7.1 GHz with a field-effect transistor (FET) configuration by measuring the two-port S-parameters under different gate bias voltages. An open-through de-embedding method has been used to extract the intrinsic properties of CNTs. A lumped-element equivalent circuit model...
This paper presents a simple equivalent circuit model to characterize a gate impedance of MOS capacitor with high-k dielectric, which exhibited significant dynamic leakage. Series of RC-shunts was added to consider the effects of charge trapping in high-k dielectric. From our model, it is found that two-frequency method using the megahertz range gives us reasonable values for the gate capacitance...
The main focus in this study is the ability to determine the CNL in Ge, defined as the crossing point where acceptor and donor-like trap densities are equal. We find CNL ~0.14 eV above the valence band edge, in good agreement with previous reports [3, 4], which locate it at 0.1 eV. The low-lying CNL is one of the essential reasons for negative charging of Ge surfaces, positive threshold voltage shift...
To achieve disturb-free writing, we proposed a new writing operation for ferroelectric-gate field-effect transistor memories with intermediate electrodes. The writing voltages VW applied to the wordlines for Pr+ and Pr0 memory states are the same pulse magnitudes, which consist of VW+ followed by VW-, whereas the bias timings of the bitline voltages differ from each other. The bitline voltage for...
The soft-error vulnerability of flip-flops has become an important factor in IC reliability in sub-100-nm CMOS technologies. In the present work the soft-error rate (SER) of a 65-nm flip-flop has been investigated with the use of alpha-accelerated testing. Simulations have been applied to study the flip-flop SER sensitivity in detail. Furthermore, an easy-to-use approach is presented to make an accurate...
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