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In this work, we designed a Visitor Counting Machine (VCM) in terms of power efficient circuit using family of three different IO Standards which are LVTTL, Mobile DDR, HSUL 12. These three different IO Standards are compared with each other on the basis of Clock power, Logic power, Signal power, IOs, Leakage power and Total power consumption to search the most power efficient one. In order to find...
It has been observed that amongst all the 22 languages being used Devanagari script is being the primary and most widely used script. Devanagari is used for writing the Hindi language in India. In this paper Energy Efficient Devanagari Unicode Reader has been designed. Devanagari is used for writing the Hindi language in India. In this paper Devanagari Unicode Reader code has been implemented on Xilinx...
In order to extend the battery life and gain in term of portability, there is always a research gap in low power processor design. In order to complete low power processor design project, there is need to re-design each and every part of processor with low power techniques. Selection of energy efficient I/O standard is also playing a significant role in energy efficient design. In this work, we are...
In print image, a watermark is an identifiable pattern which when viewed by reflected light seems to have different shades of lightness. In digital image, a watermark is a pattern, which is embedded in image to ensure the security and quality of an image. In this work, our main concern is design of energy efficient Watermark Generator (WMG) for video frame in order to gain extended life of the battery...
This paper proposes HSTL based energy efficient design of frame buffer for a digital image processor. Our aim is to make energy efficient frame buffer design and for that reason we are using different types of HSTL IO standards. This design is implemented on both Virtex-6 FPGA and Airtex-7 FPGA and compared the power dissipation. It is observed that at 1GHz operating frequency, there is maximum IO...
Power optimization is the main concern in designing. In this paper, capacitance scaling is implemented on register to optimize the power. Clock Power & Signal Power are independent of capacitance scaling. I/O Power & Leakage Power is varying with changing capacitance. There is 48.76% drop in I/O Power when we reduce capacitance from 512 pF to 256 pF. In case of reducing further to 128 pF there...
Core dynamic power is independent of output load capacitance. IO power and static power is dependent on output load capacitance. In this work, we achieved 99.72% reduction in IOs power consumption of Universal Asynchronous Receiver Transmitter (UART) if we scale down output load from 10,000pf to 5pF in IOB setting of FPGA. Universal Asynchronous Receiver and Transmitter are a transceiver circuits...
In this work, target design is ALU. To achieve reduction in IOs power we are searching the most energy efficient LVCMOS(Low Voltage Complementary Metal Oxide Semiconductor) IO standard, whose power consumption is less in compare to other IO standard. There is 85.18% power reduction when we migrate from LVCMOS33 based ALU design to LVCMOS12 based ALU design. There is 41.45% power reduction when we...
In this paper, latch free clock gating techniques is applied in ALU to reduce clock power and dynamic power consumption of ALU. Clock power is 50%, 41.46%, 51.30%, 55.15% and 55.78% of total dynamic power when device operating frequency is 100MHz, 1GHz, 10GHz, 100GHz and 1 THz. After implementation of clock gating techniques in ALU, Clock power reduces to 17.85%, 23.39%, 26.49% and 27.19% of total...
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