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In this paper we demonstrate that fast oxide trapping mechanism can be responsible for significant dynamic variability of Vt, gm and Id at circuit operating conditions. An estimation of the effect of these variabilities has been made using Monte Carlo simulations. The impact of the measured variabilities on SRAM performance is found appreciable since a margin of ~50mV in the minimum supply voltages...
This paper, for the first time, shows that the work-function variation (WFV) in emerging metal-gate devices results in significant fluctuation in the gate-oxide electric field, and hence fluctuation in bias temperature instability (BTI) characteristics (both NBTI and PBTI). We modify the existing NBTI and PBTI models in order to accurately characterize the BTI characteristics of the metal-gate devices...
Polarities of plasma charging damage in n- and p-channel MOSFETs with Hf-based high-k gate stack (HfAlOx/SiO2) were studied for two different plasma sources (Ar-and Cl-based gas mixtures), and found to depend on plasma conditions, in contrast to those with conventional SiO2. For Ar-plasma, which was confirmed to induce a larger charging damage, both n- and p-ch MOSFETs with high-k gate stacks suffer...
Reliabilities of high-k stacked gate dielectrics are discussed from the viewpoint of the impact of initial traps in high-k layer. TDDB reliability can be explained by the generated subordinate carrier injection (GSCI) model. While initial traps increase the leakage current, they do not degrade the TDDB reliability. In contrast, the BTI reliability is strongly degraded by initial traps.
Simple ring-oscillator circuit has been used to estimate the degradation in circuit performance due to negative bias temperature instability (NBTI) effect but it fails to isolate the degradation from the NBTI for PMOS and the positive bias temperature instability (PBTI) for NMOS in high-K dielectric/metal gate CMOS technology. In this paper, we propose new circuit structures which monitor the NBTI...
In this paper, bias-temperature instability (BTI) characterization on 45nm high-K + metal-gate (HK+MG) transistors is presented and degradation mechanism is discussed. Transistors with an unoptimized HK film stack in the early development phase exhibited pre-existing traps and large amount of hysteresis that was consistent with literature. The optimized and final HK process demonstrated NMOS and PMOS...
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