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Power consumption has become a key constraint in VLSI designs. Leakage current becomes a dominant part of the total power dissipation. In addition, with technology scaling into sub-50 nm regime, one of the main design challenges in the presence of process variations is to cope with the uncertainties in timing and power. Since the leakage current is highly dominated by process variations, the statistical...
The application of the conductive atomic force microscope (C-AFM) has been widely reported as a useful method of failure analysis in semiconductor field of nanometer scale science and technology, Especially for hard failure and soft failure identification and localization at logic and SRAM in CMOS process. This paper will demonstrate a new application of the C-AFM to identify the electric characteristic...
In this paper, we have investigated bulk trap and interface trap density (Dit) caused by millisecond annealing (MSA) using gate current fluctuation (GCF) and charge pumping measurements. We show that the high energy flash lamp annealing (FLA) creates the GCF with a long duration time and it is critical issue to get a stable SRAM operation. FLA creates interface traps localized at the gate edge of...
A universal test structure (UTS) for SRAM cell characterization is proposed and implemented in 65nm - 28nm technologies. The structure allows, for the first time, measurement of nearly all transistor and cell characteristics of an SRAM cell on silicon. It hence enables direct correlation among various measured transistor and cell characteristics, collection of intra-bit transistor mismatch data, and...
Ultra-scaled Z-RAM cells based on MuGFETs are demonstrated for the first time. Effects of physical parameters such as channel doping concentration, fin width, and gate length on Z-RAM cell performance are discussed. Transient measurements and simulations prove that the basic operational principles are effective on Z-RAM cells with a gate length down to 12.5 nm.
This paper reviews recent experimental confirmations that the intrinsic radiation robustness of commercial CMOS technologies naturally improves with the down-scaling. When additionally using innovative design techniques, it becomes now possible to assure that performance and radiation-hardness are both met. An illustration is given with an original nano-power and radiation-hardened 8 Mb SRAM designed...
In this paper, we investigate optimum radiation hardened by design (RHBD) for use against single-event transients (SET) using low-pass filters (LPF) including RHBD techniques against single-event upsets (SEU) for sequential logic in 45 -nm technology in a terrestrial environment. Three types of LPF were investigated regarding their SET pulse immunities, area penalties, and performance penalties. We...
The power consumption and the matching will be the principal issues at the 32 nm node and below. In this context, Ultra-Thin Body devices are extensively studied for the end-of-roadmap CMOS. In this paper we present the SON technology, leading to the simple fabrication of sustained mono-Si nano-membranes over an empty tunnel, and discuss on the application of this process to build-up electronic devices...
This paper introduces a novel current sense amplifier (CSA) in sub-32nm fully depleted (FD) double-gate (DG) silicon-on-insulator (SOI) technology with planar independent self-aligned gates. A new architecture is proposed which takes advantage of the back gate in order to improve circuit properties. Compared to the reference circuit, the new architecture proves to be faster (21% sensing delay decrease),...
Transconductance (gm) enhancement in n-type and p-type nanowire field-effect-transistors (nwFETs) is demonstrated by introducing controlled tensile strain into channel regions by pattern dependant oxidation (PADOX). Values of gm are enhanced relative to control devices by a factor of 1.5 in p-nwFETs and 3.0 in n-nwFETs. Strain distributions calculated by a three-dimensional molecular dynamics simulation...
In deep submicron era, to prevent larger amount of SRAM from more frequently encountered overheating problems and react accordingly for each possible hotspots, multiple ideal run-time temperature sensors must be closely located and response rapidly to secure system reliability while maintaining core frequency. This paper presented a method to extract run-time temperature information from multiple...
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