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This paper presents an improved, highly accurate and efficient complete analytical 4-π crosstalk noise model which incorporates all physical properties such as victim and aggressor drivers, coupling locations in both lines (victim and aggressor) and distributed RC characteristics of on-chip VLSI interconnects. In this paper, various noise avoidance approaches are explained. Sensitivity expressions...
In Deep-submicron (DSM) and Very Deep-submicron (VDSM) technologies, Scaling the minimum feature size of VLSI circuits has caused the crosstalk noise to become a serious problem, degrading the performance and reliability of high speed integrated circuits. In many digital processors and SoC interconnects and buses are dominating the silicon area than the logic. These interconnects are prone to errors...
Crosstalk noise dominates in deep submicron VLSI design as interconnects are more closely placed over a small layout area. Signal response and signal integrity is largely affected by crosstalk delay and noise. In this paper, we propose a coupled line delay model for on-chip interconnects during global routing, with crosstalk between wires as the parameter to be optimized. Our proposed model is influenced...
In DSM technology and beyond, the performance and correctness of the circuit cannot be assured without taking into consideration the multiple effects of interconnect parasitics. The inter wire parasitics i.e. mutual inductance and coupling capacitance are primary sources of crosstalk noise. In this paper, the optimization of coupling capacitance for delay and peak noise is carried out qualitatively...
With the increase in the levels of on-chip integration, the number of functional units integrated onto a single chip is rapidly increasing and as a result, the logic delays are decreasing due to faster transistors. At the same time, the local interconnect delays improve because the physical size of the circuit blocks decrease and the local interconnect spans shorter distances. On the other hand, the...
On-chip signal crosstalk is a function of switching activity pattern, coupling parasitics, and signal timing. We propose a simulated annealing (SA)-based high-level synthesis algorithm for crosstalk activity minimization for a given data environment. We target bus-based architectures as the bus-lines have well-defined neighborhood (aggressors). Our objective is to minimize worst case crosstalk patterns...
On-chip inductive effects are becoming predominant in deep submicron (DSM) interconnects due to increasing clock speed, circuit complexity and decreasing interconnect lengths. Inductance causes noise in the signal waveforms, which could adversely affect the performance of the circuit and signal integrity. The traditional analysis of crosstalk in a transmission line begins with a lossless LC representation,...
Due to the requirement of high data transmission rate, bandwidth has become an important performance parameter for high speed VLSI design. In order to have the maximum data transfer possible through the on-chip data buses, the bandwidth of the interconnect has to be precisely modeled. At very high frequency (of the order of few GHz) both inductance and conductance matrices become equally important...
For System on-chip (SoC) designs in current Deep Submicron (DSM) era, interconnects play important role in overall performance of the chip. The factors such as propagation delay, power dissipation and crosstalk through RC modeled interconnects substantially affects the entire working of the chip. Functional crosstalk and crosstalk induced propagation delay have recently emerged as major sources of...
The shrinking feature size of MOSFET devices is largely responsible for growth of VLSI circuits. In DSM technology below 0.18 μm, interconnect parasitics are significant and erupt as performance limiting parameters of the circuit. Because of short spacing between interconnects, faster signal rise time, longer wire length and use of low K-dielectric material, the coupling capacitance (CC...
Communication channels in Network-on-Chips (NoCs) are highly susceptible to crosstalk faults due to the use of nano-scale VLSI technologies in the fabrication of NoCs. Crosstalk faults cause variable timing delay in NoC channels based on the patterns of transitions appearing on the channels. This paper proposes an analytical model to estimate the timing delay of an NoC channel in the presence of crosstalk...
In this paper we have proposed a closed form delay and cross-talk noise formula for on-chip VLSI interconnect in the presence of inductive coupling. Inductive coupling effect has become an important issue in high frequency multi-layered VLSI interconnection systems. We first analytically derived the amount of crosstalk noise that would be induced on the quite victim line due to the transiting aggressor...
As the interconnect lines play an increasingly dominant role in determining circuit performance, the dynamic delay variation due to the switching activity of neighboring lines has to be accurately characterized. The goal of this work is to simulate the effect of inductance and routing orientation and then to investigate their effects on timing performances by considering three configurations of three...
VLSI circuits have become more susceptible to signal integrity related failures with the ever decreasing process geometries. Detection of crosstalk induced faults is thus important as capacitive crosstalk is one of the major sources of signal integrity related failures. Crosstalk glitch can result in erroneous output if the glitch effect propagates to a primary output or to an intermediate flip-flop...
In today's VLSI designs, crosstalk effects causing chips to fail or suffer from low yields have become one of the very essential design issues. In this paper, we attempt to reduce crosstalk noise in logic and physical synthesis stage, which is usually done in post-layout stage. We propose a technology mapping method that can reduce the crosstalk noise while meeting delay constraints. The algorithm...
On-chip interconnect delay and crosstalk noise have become an important factor for performance and signal integrity as a result of increase in device densities and operating clock frequency in deep sub-micrometer (DSM) VLSI circuits. With faster rise times and lower resistance, interconnects exhibit significant inductive effect compared to capacitive effect. Therefore, various existing coding techniques...
Decreasing process geometries and increasing operating frequencies have made VLSI circuits more susceptible to signal integrity related failures. Capacitive crosstalk is one of the major causes for such kind of failures. Typically, crosstalk faults result from switching of neighboring lines that are capacitively coupled. As we move deep into nanometer regime, transistor gate leakage introduces considerable...
Crosstalk faults have emerged as a significant mechanism for circuit failure. Long signal nets are of particular concern because they tend to have a higher coupling capacitance to overall capacitance ratio. A typical long net also has multiple aggressors. In generating patterns to create maximal crosstalk noise on a net, it may not be possible to activate all aggressors logically or simultaneously...
In this paper a technique has been introduced for reducing crosstalk for restricted channel routing. First, the random channel specification is generated. After that the adjacency matrix of the corresponding random channel specification is created and the horizontal constraint graph (HCG) is drawn. Using the existing graph coloring algorithm and the Genetic Algorithm (GA) the HCG is tinted. The minimum...
With rapid advances in VLSI, technology has enabled us to reduce the minimum feature sizes of sub-quarter microns and the switching times to tens of picoseconds or even less. The trend in VLSI industry is moving toward designs that are more complex, higher operating frequencies, sharper rise times, shrinking device sizes and low power consumption. Although the device noise sources (i.e. shot noise,...
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