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The design and implementation of a multitasking run-time system on a tightly coupled FPGA-CPU platform is presented. Using a mix of CPU and FPGA programmable logic for computing, user applications are executed as mixed-architecture processes from the perspective of the OS. Context switching mechanisms with hybrid scheduling containing both blocking and preemption support were implemented to support...
High-speed power gating (PG) techniques are useful for reducing leakage power of functional units in a CPU core. This paper analyzes trade off of functional units in a MIPS R3000 based processor with three fine-grained PG methods: the cell-based, row-based and ring-based. Compared with the cell-based PG technique, which was used in our previous work - Geyser-1 processor, the row-based and ring-based...
Geyser-1, a prototype MIPS R3000 CPU with fine grain runtime PG for major computational components in the execution stage is available. Function units such as CLU, shifter, multiplier and divider are power-gated and controlled at runtime such that only the function unit to be used is powered-on to minimize the leakage power. The evaluation results on the real chip reveals that the fine grain runtime...
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