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This paper presents implementation of fault emulation method which is very important in today's chip tests on a platform with heterogeneous architecture. Nowadays, the increase in the number of transistors in electronic circuits put fault emulation method forward which is faster than fault simulation in order to obtain a test set against possible defects on chips. In this method, a hardware model...
GPUs have emerged as general-purpose accelerators in high-performance computing (HPC) and scientific applications. However, the reliability characteristics of GPU applications have not been investigated in depth. While error propagation has been extensively investigated for non-GPU applications, GPU applications have a very different programming model which can have a significant effect on error propagation...
An unconventional software testing method, fault injection based on fault model, is enhanced to improve the software reliability testing and measurements. Dynamic fault models for injecting faults through software are investigated and reported in this paper including memory faults, CPU faults and communication fault models. Dynamic fault models can be used to simulate influences which are caused by...
In this paper, we propose a new low capture power test generation method based on fault simulation to reduce the number of unsafe faults. The method uses capture-safe test vectors in an initial test set to generate new test vectors. Our experimental results show that the use of this method reduces the number of unsafe faults by 94% on average, and while requiring less test generation time compared...
Fault Diagnosis is a critical process to identify the locations of physical defects in advanced integrated circuits. Current diagnosis tools often report multiple types of faults as defect candidates. Thus an efficient method to distinguish different types of faults is highly desired. Stuck-at and bridging faults are two most commonly used DC fault models during diagnosis. In this paper we present...
This paper proposes an efficient diagnosis-aware ATPG method that can quickly identify equivalent-fault pairs and generate diagnosis patterns for nonequivalent-fault pairs, where an (non)equivalent-fault pair contains two stuck-at faults that are (not) equivalent. A novel fault injection method is developed which allows one to embed all fault pairs undistinguished by the conventional test patterns...
This paper investigates a novel modular approach to efficiently estimate the Architectural Vulnerability Factor (AVF) of large designs by employing circuit partitioning and error propagation techniques. Modular approach is a hybrid of statistical fault injection technique and analysis based technique. Results show that for the same level of accuracy, our modular approach arrives at the AVF within...
Boundary scan test is a standard measurability design technology, and it is more convenient for the measurement of complex circuits. Based on the basic principle of boundary scan and one system's CPU board, the boundary scan design and configuration of the system's control circuit are presented and validated. According to the experiments of the designed CPU, the circuit can realize the functions of...
Semiconductor industry has come to the era to rely heavily on detecting small-delay defects (SDDs) for high defect coverage of manufactured digital circuits and low defective parts per million (DPPM). Traditional timing-unaware transition-delay fault (TDF) ATPGs are proven to be inefficient in detecting SDDs. The commercial timing-aware ATPGs have been developed for screening SDDs, but they suffer...
We propose a roll-forward error recovery technique based on multiple scan chains for TMR systems, called Scan chained TMR (ScTMR). ScTMR reuses the scan chain flip-flops employed for testability purposes to restore the correct state of a TMR system in the presence of transient or permanent errors. In the proposed ScTMR technique, we present a voter circuitry to locate the faulty module and a controller...
Faster than at-speed testing provides an effective way to detect small delay defects (SDDs). It requires test patterns to be delicately classified into groups according to the delay of sensitized paths. Each group of patterns is applied at certain frequency. In this paper, we propose to generate tests for faster than at-speed testing using path delay fault (PDF) model and single path sensitization...
A diagnostic automatic test pattern generation (DATPG) system is constructed by adding new algorithmic capabilities to conventional ATPG and fault simulation programs. The system generates tests to distinguish between fault pairs through different output responses. Given a fault pair, by modifying circuit netlist a new single fault is modeled and targeted for detection by a conventional ATPG. The...
Redundancy Addition and Removal (RAR), one of the major combinational logic perturbation techniques, has been shown to be very useful for many EDA optimization tasks. However, all the currently known RAR techniques did not analyze and make use of unreachable states, which are abundant in sequential circuits. These unreachable states can be considered as input don't cares and can add an extra flexibility...
The middle-low voltage distribution networks mostly adopt neuter point not-valid grounding(be so called to the small current groundding system).The distribution wire fault particularly the fast and accurate location that the single grounding fault, not only to the repair wire and promise dependable power supply, and circulate to the safe stability and economy that promises the whole electric power...
The paper deals with the problem of testing CPUs in embedded systems taking into account application properties. Basing on the developed original software tools we have analysed the coverage of CPU functionality and operational stresses for many benchmark programs. The experimental results confirmed the need of introducing application driven testing of CPUs to assure high fault coverage with acceptable...
Testing for small-delay defects requires fault-effect propagation along the longest testable paths. However, the selection of the longest testable paths requires high CPU time and leads to large pattern counts. Dynamic test compaction for small-delay defects has remained largely unexplored thus far. We propose a path-selection scheme to accelerate ATPG based on stored testable critical-path information...
PCB fault detection and positioning is always a complex and difficult work. This thesis designed a fault diagnosis system for PCB circuit, which uses voltage signals as incentive signals and the voltage or current response signals as the output. Fault tree is established and fault searching and positioning method introduced fault dictionary analysis according to the fault tree. Through simulation...
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