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A 3rd order continuous time (CT) Sigma-Delta modulator with a 14-level flash quantizer is presented, which achieves a resolution of 11.2 bit (ENOB) and a SFDR of 84.6 dB for a signal bandwidth of 12.5 MHz according to transistor level post-layout simulations. The proposed solutions limit the total power consumption to 11.3 mW at a supply voltage of 1.2 V with a UMC 0.13 μm CMOS process.
This paper presents the design of a highly efficient CMOS level shifter qc-level shifter. Unlike many recent level shifters, the proposed qc-level shifter does not use bootstrap capacitors to minimize active area. When implemented on a 65 nm CMOS technology, under the large capacitive loading condition (2pF), qc-level shifter has a lower active area (94%), and energy-delay product (21.4%) than the...
This paper presents the design of a highly energy efficient CMOS adiabatic driver (ob-driver). The proposed ob-driver uses an output stage with two inverters driven by a pre-driver circuit consisting of two differential cascode voltage switch (DCVS) logic cells. When implemented on a 0.13 mum CMOS 1.2V technology, under the large capacitive loading condition, ob-driver performs better than the reference...
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