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In this publication, we discuss the recent upgrade of the intermediate power amplifier (IPA) of the 520 MeV Cyclotron's RF system. The main goal of this upgrade was to separate first and second stages of the IPA, and thus achieve a modular configuration. A novel neutralization circuit for the second stage was designed, simulated, fabricated and tested with maximal CW power of up to 65 kW. We discuss...
A 4.6–5.6 GHz constant KVCO LC-VCO applied in PLL frequency synthesizer is presented in this paper. With constant KVCO LC-VCO and programmable charge pump, the frequency synthesizer is able to obtain constant bandwidth. Furthermore, the VCO has a low KVCO which will result low phase noise. An Optimized automatic frequency calibrator (AFC) is proposed, the AFC can select the sub-band which is nearest...
The symmetrical compensation is widely used in inductive power transfer (IPT) system due to the advantages of achieving good coupling coefficient when the coils are perfectly aligned and easy to design. This paper investigates a general tuning method for voltage-fed symmetrical higher-order resonant networks for achieving load-independent transconductance. With the proposed tuning method, a resonant...
A wide range current controlled CMOS transconductor is presented. The proposed circuit relies on a current controlled current amplifier that uses an unbalanced current mirror. A fifth-order Butterworth low pass filter based on the novel transconductor is also presented as application.
This paper presents a multi-PLL clock architecture used in a 4-lane multi-protocol serial link applications. The clock architecture consists of one public LC PLL and four standalone ring PLLs placed within each lane. A swtich capacitor array based LC VCO is used in the LC PLL to enlarge the frequency tuning range and decrease the VCO gain. A two stage pseudodifferential inverter based ring VCO with...
A class-C VCO with dual negative feedback architecture is proposed to break the trade-off between amplitude stability of oscillation and bias current flicker noise. Inherent dynamic biasing of this architecture maximizes available voltage swing and provides robust current control without any additional circuits. To inject current exactly at the peak of oscillation, a capacitive feedback technique...
This paper presents a wideband LC PLL designed for multi-protocol serial link applications. Dual LC voltage controlled oscillator (VCO) cores are used to cover a wide frequency range while keeping a high Q factor of the LC tank, and multi-ratio dividers are used to satisfy the multi-protocol requirements. Each LC VCO adopts a 4-bit switch capacitor to increase the frequency tuning range and decrease...
This paper presents a novel architecture for a kilo-ohm to giga-ohm pseudo-resistor (PR), based on transistors operating in subthreshold with a fixed-Vgs configuration. This PR when used in an RC filter has a very low and constant settling time regardless of the programmed pole frequency. The proposed PR takes advantage of bootstrapping to improve its tuning range. By defining a constant VGs for the...
In this paper a side-channel-attack resistant AES system with a variation-tolerant true Random Number Generator (tRNG) is implemented using IBM 0.13μm CMOS technology. As the random source for the AES, a meta-stability based tRNG takes advantage of an all-digital self-calibration method to compensate Process-Voltage-Temperature (PVT) variations, and thus guarantees output with extremely high randomness...
This paper presents the design and implementation of a CMOS transformer combiner that can be reconfigured to have similar efficiencies at widely separated frequency bands. Conventional transformer combiners employ a fixed tuning capacitance in the secondary network to optimize the efficiency for single frequency standard. In this work, we present a modified transformer combiner where digitally-switchable...
This paper presents a low power consumption LC-tank voltage controlled-oscillator (VCO). It is suitable for communication system of Integrated circuit. In this circuit, the operating frequency is generated by LC-tank. The circuit add a forward-bias circuit at the body to decrease the threshold voltage. Therefore, it can reduce the operation voltage and minimize the dc power consumption. This design...
Wireless-powered chips are used in a wide range of applications, including biomedical implants. However, the resonant frequency of the power receiving circuit can be affected not only by process variations, but also by the changing environment. In order to optimize the power transfer and allow the chip to work despite these variations, a fully integrated tuning system is proposed. After having assessed...
A low-voltage high-swing voltage-biased Colpitts voltage-controlled oscillator (VCO) is proposed for wireless applications. A small capacitive voltage divide factor is chosen to enhance the output swing and improve the phase noise performance. To further enhance the negative resistance, and thus decrease the start-up time, the bulk terminals of the gm-boosting transistors are dynamic-biased by the...
The ability to identify (detect) and categorise (sort) neural spikes in real-time and under highly restrictive power/area budgets is a major enabling technology towards the development of intelligent implantable systems. In this work we propose a memristor-CMOS hybrid architecture concept that relies on a ‘template pixel’ (texel) circuit combining CMOS and memristive devices to perform on-line spike...
This paper proposes a new type of delay line locking mechanism with digitally controlled charge transfer. Delay-locked loop (DLL) based on the presented method features multi-phase outputs and is stepwise driven towards lock by a co-action of 1-bit Time-to-Digital Converters and revised charge-pump. On-chip pulse “slicing” arrangement provides high-rate clock for the Digital Signal Processing algorithm,...
This paper presents the implementation of a self-test for a gyroscope readout based on electro-mechanical ΔΣ modulation. Commonly, sensor element and readout ASIC are fabricated on separate wafers. Therefore, the ability to characterize sensor element and ASIC before packaging is desirable in order to reduce unnecessary expense. For the proposed self-test, a charge integrator with collocated detection...
This paper presents the design and simulation of an auto-tuning capacitive power transfer (CPT) system based on Class-E converter approach. The reason of selecting Class-E converter is due to the remarkably high efficiency that it can achieve. However, the load's variation affects the output voltage of Class-E converter significantly and increases the switching loss of the system. To regulate the...
This paper reports 2.37–5.94 GHz multicore CMOS LC Digitally-Controlled Oscillator (DCO) designed in 65 nm RF CMOS technology. The three cores of 6-bit switch capacitor array provides wide LC-DCO tuning range. With 1.8 V supply voltage, simulation results show that the tuning range is from 2.37 GHz to 5.94 GHz, while average phase noise value across the entire tuning range is −135 dBc/Hz. Power dissipation...
Characterization of a tunable electric-LC resonator is presented in this work. The tuning is obtained through using liquid crystal material in the central capacitor gap. Fitting the resonator with an interdigital capacitor, increases the total capacitance of the structure as well as the tuning range. An equivalent circuit model synthesis is proposed to simplify the design procedure of the FSS. The...
This paper presents the design and characterization of a miniaturized tunable bandpass filter utilizing high-Q ceramic coaxial resonators and commercially available RF-MEMS tunable digital capacitors. A proof-of-concept 2-pole tunable filter occupying only 10 × 10 mm2 is demonstrated with a frequency tuning range of 800–1100 MHz and bandwidth tuning range of 6–13%.
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