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ECC techniques have been widely used for protecting flash memory endurance and permanent faults. Therefore, the fabrication yield and reliability can be enhanced. However, if the number of faulty bits within a codeword is greater than the protection capability of the adopted ECC techniques, the effectiveness of the protection will decrease rapidly. In this paper, adaptive ECC techniques based on address...
Error correction code (ECC) and hard repair (built-in self-repair) techniques by using redundancies have been widely used for improving the yield and reliability of memories. The target faults of these two schemes are soft errors and permanent faults, respectively. In recent works, there are also some techniques integrating ECC and BISR to deal with soft errors and hard defects simultaneously. However,...
This paper presents a scalable hardware architecture for permanent fault compensation in arbitrary processor components. The utilization of this architecture is independent from the fault case and is therefore suitable for fault compensation after production as well as in the field. Through the application of this architecture, based on active hardware redundancy, a gain in reliability for a specified...
Fault scrambling technique is considered a promising way to distribute faulty bits into different code words such that the number of faulty cells in each codeword is below the protection capability of the adopted EDAC coding techniques. However, the effectiveness of the scrambling technique depends on the determination of the row/column scrambling control words. Therefore, we propose a heuristic algorithm...
In response to reliability challenges of new systems being built, we are proposing a scalable Self-Test architecture for many-core processor systems. This BIST architecture periodically distributes test stimuli among identical processing cores in a many-core processor system, suspends normal operation of individual processing cores, applies test, detects faulty cores, and removes them from the system...
Current technology scaling enables the integration of tens of processing elements into a single chip, and future technology nodes will soon allow the integration of hundreds of cores per device. While very powerful, many experts agree that these systems will be prone to a significant number of permanent and transient faults during their lifetime. If not properly handled, effects of runtime failures...
A large class of robust electronic systems of the future must be designed to perform correctly despite hardware failures. In contrast, today's mainstream systems typically assume error-free hardware. Classical fault-tolerant computing techniques are too expensive for this purpose. This paper presents an overview of new techniques that can enable a sea change in the design of cost-effective robust...
Technology scaling inevitably leads to fabrication processes, which are more susceptible to production faults. At the same time, devices become more vulnerable to wear-out effects, which reduce the long term system reliability. The upcoming challenge of future designs is the development of integrated test and repair techniques dealing with both types of fault mechanisms. Our paper presents a built-in...
Concurrent autonomous self-test, or online self-test, allows a system to test itself, concurrently during normal operation, with no system downtime visible to the end-user. Online self-test is important for overcoming major reliability challenges such as early-life failures and circuit aging in future System-on-Chips (SoCs). To ensure required levels of overall reliability of SoCs, it is essential...
Robust system design ensures that future systems continue to meet user expectations despite rising levels of underlying disturbances. This paper discusses two essential aspects of robust system design: 1. Effective post-silicon validation, despite staggering complexity of future systems, using a new technique called Instruction Footprint Recording and Analysis (IFRA). 2. Cost-effective design of systems...
In this paper we propose an on-line self-test architecture for hardware implementations of advanced encryption standard (AES). The solution assumes a parallel architecture and exploits the inherent spatial replications of this implementation. We show that our solution is very effective for on-line fault detection while keeping the area overhead very low. Moreover, it does not weak the device with...
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