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Analog-to-Digital Converts (ADC) are becoming essential to the function of ultra-high speed interconnects (IO) with complex modulation schemes, while at the same time reduction in supply voltage has negatively impacted the performance of such circuits. However the improvement in delay times and reduction in logic size has made time-based ADCs attractive. To accomplish this, a Voltage-to-Time Converter...
Analog-to-digital converters (ADCs) are needed in all those applications, which interface with the analogue world and exploit the digital processing of data. As digital processing is more and more gaining ground over analogue signal processing, the importance of ADCs correspondingly increases. The Flash type ADC, also known as Direct Conversion ADC, uses a bank of comparators, operating in parallel...
This paper presents the application of body biasing to improve linearity performance of CMOS Gilbert-cell mixers. In order to improve the linearity, the bulk bias voltage of the transistors in the local oscillator (LO) stage is adjusted. The improvement in linearity is obtained while the conversion gain and power consumption of the mixer remain virtually intact. A 0.13-µm CMOS proof-of-concept prototype...
An analysis of a cascode source-follower with all transistors operating in saturation mode is presented. The new structure provides means to mitigate the effects of nonlinearities caused by transistor capacitances. It is also studied the effects of adding a sampling switch at the output of the source-follower. Performance results of 0.35µm CMOS implementation and dimensioning methodology of the resulting...
In this paper a high frequency low voltage low power tunable highly linear transconductor is presented. Shift level biasing is used at the inputs of both the amplifiers of a cross coupled differential pair for tuning. Bias currents of cross coupled differential amplifiers are adjusted to cancel third harmonic distortion. The proposed circuit is simulated in Cadence VIRTUOSO environment with UMC 0...
This work focuses on a new compact 6-transistor CMOS temperature sensor with improved flexibility for achieving target temperature linearity with small die area and low power consumption. The temperature information is provided in a differential output voltage that is based upon the linear dependence of threshold voltage on temperature. Implemented in a 0.18μm process, simulation results indicate...
A 0.5 μm CMOS floating voltage-controlled resistor with wide resistance dynamic range and low supply voltage is presented. The current inputs of two second generation current conveyors are loaded by non-saturated MOSFET with controllable resistance. Both a quasi rail-to-rail operation and a wide resistance dynamic range, with large resistances, are achieved using the input signal adapters. For a single...
A new linearization technique for CMOS low-noise amplifiers (LNAs) based on body biasing is presented. Analysis and measurement results show that the third order intercept point (IIP3) can be optimized using a proper body bias. The LNA, intended for wireless sensor network applications in the 2.4 GHz ISM Band, is implemented in a 0.13 ??m CMOS technology. It achieves a nominal gain of 12.6 dB, 4.2...
In this paper a new CMOS current-mode four-quadrant analog multiplier circuit based on squarer circuit is proposed. The dual translinear loop is the basic building block in realization scheme. Supply voltage is 3.3 V. The major advantages of this multiplier are high speed, low power, high linearity and less dc offset error. The circuit is designed and simulated using HSPICE simulator by level 49 parameters...
This paper presents fully differential up-and down-conversion mixers manufactured in a triple well 45 nm standard CMOS process for low voltage UWB TX and RX applications. The proposed circuits both employ the transistor bulk terminal for signal injection. While the RX mixer uses the bulk for switching via threshold voltage modulation, the TX mixer applies the baseband signal to the bulk. Both circuits...
A high intercept points, cost-effective, and power-efficient switching FET double balanced mixer (DBM) is reported. The Switching FET DBM demonstrated in this work offers input intercept points (IIP3) and conversion loss typically 44 dBm and 8.5 dB respectively with 15 dBm LO power for the frequency band (RF: 900-2150 MHz, LO: 850-1950 MHz, IF: 50-200 MHz). The measured interport isolation is typically...
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