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The computational complexity of the finite difference (FD) schemes for the solution of the plate equation prevents them from being used in musical applications. The explicit FD schemes can be parallelized to run on multi-processor arrays for achieving real-time performance. Field Programmable Gate Arrays (FPGAs) provide an ideal platform for implementing these architectures with the advantages of...
Conjugate Gradient method is a very efficient iterative method for solving large systems of equations arising from real life scientific computing applications. In this paper we present the Conjugate Gradient method and its variants in brief. We also present a comparative analysis of implementations of this method on various platforms like FPGAs, GPUs etc which are suitable for High Performance Computing.
In hw/sw co-design FPGAs are being used in order to accelerate existing solutions so they meet real-time constraints. As they consume less power than a standard microprocessor and provide powerful parallel data processing capabilities, they remain a highly optimizable tool and object of research within an embedded system. In this paper we present an efficient architecture for matrix multiplication...
Dynamic Circuit Specialisation (DCS) is a method that exploits the reconfigurability of modern FPGAs to allow the specialisation of FPGA circuits at run-time. Currently, it is only explored as part of Register-transfer level design. However, at the Register-transfer level (RTL), a large part of the design is already locked in. Therefore, maximally exploiting the opportunities of DCS could require...
Adders play an important role in digital circuits. Logarithmic adders are efficient in delay reduction of carry generation/propagation in contrary to linear adders. It is found from simulations that even logarithmic adders suffer from delay, chip area over head and additional latches in the presence of ripple carry adders at the time of FPGA realization. The main motive of this work is to design and...
Fault detection and correction algorithms has been widely adopted in the various data communication system with view to protect the system from crashing due to hard and soft errors. As the system becomes more complex with the reduction of transistor size, fault detection and correction schemes are not limited to data transfer process. Internal components of the system's processor are also susceptible...
Wireless communication systems are dense compositions of signal processing and VLSI technologies. Due to increase in demand of higher data rate and better quality of services, VLSI design and implementation method for wireless communication becomes more challenging. Multiple-input and multiple-output (MIMO) technique is rapidly increasing in the last decade which provides higher throughput at no additional...
Efficient algorithms for the continuous representation of a discrete signal in terms of B-splines and for interpolative signal reconstruction have been proposed in this paper. It analyzes the relationship between the degree of the spline and the quality of the interpolation. By taking the z-transforms of the sampled B-spline functions, a fast interpolation algorithm based on digital filters of IIR...
This paper proposes a parallel fixed point radial basis function (RBF) artificial neural network (ANN), implemented in a field programmable gate array (FPGA) trained with a least mean square (LMS) algorithm. The processing time and occupied area were analyzed for various fixed point formats. The problems of precision of the ANN response for nonlinear classification using the XOR gate, and interpolation...
This tutorial paper presents the concepts of sliding mode controller (SMC) and sliding mode observer(SMO) design for different DC/DC converters. Design and implementation aspects, using FPGA, of sliding mode controller and sliding mode observer for three basic topologies of DC/DC converters are discussed. Sliding Mode Control, an established technique for control and estimation, is implemented for...
This paper presents an FPGA-based real-time simulation system of a nonlinear permanent magnet synchronous machine and its qualification for power hardware-in-the-loop emulation systems. The machine model considers the magnetic anisotropy of the rotor, the saturation of the iron as well as dynamic cross-coupling effects between the direct- and quadrature axis of the machine. A specifically designed...
Space-Time Adaptive Processing (STAP) technique can restrain the effects of interference and clutter effectively. However, the calculation of STAP weights, including QR decomposition (QRD) and solving linear equations needs intensive computation. This paper mainly focuses on improving the QRD algorithm and presents an efficient FPGA design, based on floating point IP core, which can meet the requirement...
In this paper, we discuss and evaluate about a grain size of the PE of a matrix operation specific architecture with fused multiply add (FMA) units, Rapid MatriX, on FPGAs. Recent FPGAs have many DSP blocks which are high-performance arithmetic units. Hereby, implementing functional units for matrix operation to array structure of the Rapid MatriX, we propose to use DSP blocks efficiently by increasing...
Scrubbing has been considered as an effective mechanism to provide fault-tolerance in Static-RAM (SRAM)-based Field Programmable Gate Arrays (FPGAs). However, the current scrubbing techniques execute without considering the criticality and timing of the user tasks implemented in the FPGA. They often do not execute the scrubbing process in the right instant, which minimizes the probability of each...
Atmospheric modeling is an essential issue in the study of climate change. However, due to the complicated algorithmic and communication models, scientists and researchers are facing tough challenges in finding efficient solutions to solve the atmospheric equations. In this paper, we accelerate a solver for the three-dimensional Euler atmospheric equations through reconfigurable data flow engines...
In this paper, we present a hardware architecture for implementing an interior point method for model predictive control (MPC) on field programmable gate arrays (FPGA). The FPGA implementation allows the solution of quadratic programs occurring in MPC at very high speed. Experiments show that our hardware implementation is able to outperform an software implementation running on a high-end CPU while...
Readback scrubbing is considered as an effective mechanism to correct errors in Static-RAM (SRAM)-based Field Programmable Gate Arrays (FPGAs). However, current solutions have a low error correction percentage per unit area overhead. This paper proposes two new error detection/correction mechanisms that combine frame readback scrubbing with error correction codes (ECCs) that are applied in multiple...
This paper presents a design that forms the framework of an acoustic positioning system. The FPGA core system installed within any mobile target uses the passive architecture, which is selected to lengthen the lifetime of battery and to preserve location privacy. The mobile target can be tracked by detecting particular acoustic signals sent from moored transponders. The whole design is accomplished...
In Digital Image Processing, the discrete linear convolution is used as a basis for linear filtering. In this paper, the multiplier operation involved in discrete linear convolution operation using CORDIC and Vedic algorithm is implemented on FPGA Spartan XC3S1000 device. Performance evaluation of these two approaches is done and the trade off in terms of Area, Power and Speed is tabulated. It is...
Cryptographic hash functions have many security based applications, particularly in message authentication codes (MACs), digital signatures and data integrity. Secure Hash Algorithm-3 (SHA-3) is a new cryptographic hash algorithm that was selected on 2nd Oct '12 after a five year public contest organized by the National Institute of Standards and Technology (NIST), USA. This paper provides a unique...
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