The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Hardware-in-the-loop (HIL) simulation is an industrial practice that consists in testing a physical electronic control unit (ECU) against a real-time simulated model of a plant. Typical PWM applications run in the kHz range and can hardly be simulated using standard methods with the typical CPU time-steps that are at best in the 5-10 microseconds range. Migrating the computational load from a CPU...
Algorithms for biological sequence analysis, such as approximate string matching or algorithms for identification of sequence patterns supporting specific structural elements, present good opportunities for hardware acceleration. Implementation of these algorithms often results in architectures based on multidimensional arrays of computing elements. Mapping effectively these computational structures...
In this work, we propose a design and FPGA (Field Programmable Gate Arrays) implementation of two parallel architectures for majority logic decoder of low complexity for high data rate applications, These architectures are hard decision architecture (Hard in — Hard out (HIHO)) and the SIHO threshold decoding. The code used is the Difference Set Cyclic code (DSC (21, 11)). The VHDL (Very high speed...
The article deals with the design, simulation and implementation of QDEC (Quadrature Decoder) machine with increased reliability (QDEC2) for implementation in a programmable FPGA (Field Programmable Gate Array) circuit. The purpose of research activities of reliable QDEC2 in the FPGA is the incorporation of this model to control of the robot. In the first part of the article describes the possibility...
Estimating the power consumption of System on Chip as early as possible in the design life cycle is important to meet the time to market requirements. For this purpose, most research is turning toward high-level models, like TLM, to estimate power earlier. This paper presents a high-level IP oriented power estimation methodology. The methodology separates the activity of the IP from the implementation...
The fuzzy controller implemented in Field Programmable Gate Array (FPGA) for a fuel cell generation system is presented in this paper. The fuel cell generation system which is considered for the study consists of a stack, reformer, DC-DC converter and loads. Under the demands on control in application of the converter, a fuzzy controller used to manage the power flow was presented. Paralleling fuzzy...
Mathematical modeling and simulation of cellular systems are important processes in modern life science, to understand the behavior of life as a system. Kinetic model of a biochemical pathways is described as an ordinary differential system, consists of a variety of equations to represent velocity of corresponding chemical reactions. This paper describes a modular and automated approach to synthesize...
This paper describes an analytical model, based principally on Rentpsilas Rule, that relates logic architectural parameters to the area efficiency of an FPGA. In particular, the model relates the lookup-table size, the cluster size, and the number of inputs per cluster to the amount of logic that can be packed into each lookup-table and cluster, and the number of used inputs per cluster. Comparison...
Window operations which are computationally intensive and data intensive are frequently used in image compression, pattern recognition and digital signal processing. Reconfigurable hardware boards provide a convenient and flexible solution to speed up these algorithms. This paper studies the effect of loop unrolling on the area, clock speed and throughput based on a data schedule method to find the...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.