The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Adders play an important role in digital circuits. Logarithmic adders are efficient in delay reduction of carry generation/propagation in contrary to linear adders. It is found from simulations that even logarithmic adders suffer from delay, chip area over head and additional latches in the presence of ripple carry adders at the time of FPGA realization. The main motive of this work is to design and...
Wireless communication systems are dense compositions of signal processing and VLSI technologies. Due to increase in demand of higher data rate and better quality of services, VLSI design and implementation method for wireless communication becomes more challenging. Multiple-input and multiple-output (MIMO) technique is rapidly increasing in the last decade which provides higher throughput at no additional...
Efficient algorithms for the continuous representation of a discrete signal in terms of B-splines and for interpolative signal reconstruction have been proposed in this paper. It analyzes the relationship between the degree of the spline and the quality of the interpolation. By taking the z-transforms of the sampled B-spline functions, a fast interpolation algorithm based on digital filters of IIR...
This tutorial paper presents the concepts of sliding mode controller (SMC) and sliding mode observer(SMO) design for different DC/DC converters. Design and implementation aspects, using FPGA, of sliding mode controller and sliding mode observer for three basic topologies of DC/DC converters are discussed. Sliding Mode Control, an established technique for control and estimation, is implemented for...
Space-Time Adaptive Processing (STAP) technique can restrain the effects of interference and clutter effectively. However, the calculation of STAP weights, including QR decomposition (QRD) and solving linear equations needs intensive computation. This paper mainly focuses on improving the QRD algorithm and presents an efficient FPGA design, based on floating point IP core, which can meet the requirement...
In this paper, we discuss and evaluate about a grain size of the PE of a matrix operation specific architecture with fused multiply add (FMA) units, Rapid MatriX, on FPGAs. Recent FPGAs have many DSP blocks which are high-performance arithmetic units. Hereby, implementing functional units for matrix operation to array structure of the Rapid MatriX, we propose to use DSP blocks efficiently by increasing...
Atmospheric modeling is an essential issue in the study of climate change. However, due to the complicated algorithmic and communication models, scientists and researchers are facing tough challenges in finding efficient solutions to solve the atmospheric equations. In this paper, we accelerate a solver for the three-dimensional Euler atmospheric equations through reconfigurable data flow engines...
This paper presents a design that forms the framework of an acoustic positioning system. The FPGA core system installed within any mobile target uses the passive architecture, which is selected to lengthen the lifetime of battery and to preserve location privacy. The mobile target can be tracked by detecting particular acoustic signals sent from moored transponders. The whole design is accomplished...
In Digital Image Processing, the discrete linear convolution is used as a basis for linear filtering. In this paper, the multiplier operation involved in discrete linear convolution operation using CORDIC and Vedic algorithm is implemented on FPGA Spartan XC3S1000 device. Performance evaluation of these two approaches is done and the trade off in terms of Area, Power and Speed is tabulated. It is...
Cryptographic hash functions have many security based applications, particularly in message authentication codes (MACs), digital signatures and data integrity. Secure Hash Algorithm-3 (SHA-3) is a new cryptographic hash algorithm that was selected on 2nd Oct '12 after a five year public contest organized by the National Institute of Standards and Technology (NIST), USA. This paper provides a unique...
Today, the stereoscopic 3D movie is already mainstream, and almost all new devices support stereoscopic 3D movie. The content generation and the necessity to wear glasses, however, hinder the broader acceptance of the technology. Audiences who have poor vision prefer to the glasses free stereoscopic movie. Multi-view video enables a glasses free perception of stereoscopic 3D movie. To support this,...
We developed a square wave based artificial neuron to take advantage of inexpensive and readily available Field Programmable Gate Array technologies. While conventional neurons require computationally intensive floating point arithmetic to determine the output, our artificial neuron converts inputs into square waves and the time that these waves require to produce a predetermined bit pattern is used...
Run-time reconfiguration has the potential to allow reuse of resources and the reduce cost of FPGA-based systems. To compute feasible placement locations for PR modules in such systems, multiple constraints have to be evaluated. This includes unused area, placement of heterogeneous resources and communication requirements of the PR module. To improve resource utilization, both polyomino shaped PR...
We propose a novel approach to the computation of the CRC functions, commonly used for bit error checking purposes when handling binary data. This approach is designed for general hashing purposes in FPGA, for which the CRCs are usable as well. The method is suitable for applications which use parallel inputs of fixed size and require high throughput, such as hash tables. We employ the DSP blocks...
In design and implementation of energy efficient register, we are using different I/O standard in 28nm Artix-7 FPGA, Verilog, Xilinx ISE 14.6 as simulator and XPower 14.6 as energy estimator and analyzer tool. This register is a building block of energy efficient processor based on LVCMOS (Low Voltage Complementary Metal Oxide I/O, HSTL(High Speed Transistor Logic), HSUL standard in FPGA. This design...
This paper discusses the implementation of math hardware module based on CORDIC algorithm to solve trigonometry, hyperbolic and exponential function on FPGA. CORDIC is one of the hardware efficient and iteration based algorithms that is used to implement various transcendental functions such as trigonometry, hyperbolic, exponential and so forth. In addition, by using this algorithm, the hardware requirement...
Cholesky decomposition has wide applications in solving many engineering and scientific problems. Acceleration is an important issue in many of these problems. In this paper, a hardware-based LLT Cholesky decomposition featuring high throughput has been presented to solve wiener filtering based on the minimum square error criterion. To achieve the best efficiency, the hardware-based implementation...
This paper presents an efficient and scalable implementation of an FPGA-based accelerator for sliding-window aggregates over disordered data streams. With an increasing number of overlapping sliding-windows, the window aggregates have a serious scalability issue, especially when it comes to implementing them in parallel processing hardware (e.g., FPGAs). To address the issue, we propose a resource-efficient,...
Modular addition is a widely used operation in Residue Number System applications. Specific sets of moduli allow fast RNS operations such as binary conversions and multiplications. Most of them use modulo 2n − 1 and 2n ; 1 additions. This paper presents four fast and small architectures for these specific moduli targeting modern FPGAs with fast carry chains. The use of this arithmetic dedicated feature...
This paper presents a new approach to vector PMSM control implemented on a FPGA platform with a soft processor core integration for floating point computation. An advanced vector control is developed, according to PMSM vector control state-of-the-art, where the torque reference is a direct input to the system, dynamically controlling the injection of stator current flux component, in order to direct...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.