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The number of IPs running concurrently on an FPGA has increased in recent years. Communication among these IPs has necessitated the introduction of the network on chip (NoC) for low-power, high-performance, and scalable on-chip networking. While NoCs are superior to traditional shared buses, there is an attendant resource overhead incurred by the NoC links, routers and network adapters. We present...
With the advancements in the hardware technology, it is now possible to transmit data over Ethernet at the rate of 100Mbps/1Gbps. The only limiting factor for such a high peed data transfer is the speed of the processor in the computer which does all the TCP/IP processing by using the TCP/IP software written in it. In the present system, the IR sensor used is taking 50 images of plasma per second...
A system implementation framework is presented for configurable high-speed IP over AOS gateway in this paper. Pipeline operation and asynchronous FIFOs are adopted to achieve rate matching and data synchronization between different clock domains. The format of configuration packet of IP over AOS gateway and finite state machine description of protocol are given. The simulation results show that the...
Mixed architectures which contain both programmable devices and reconfigurable ones provide a powerful solution to meet the computational requirement of newest digital signal processing applications. But they are so complex that their design is slow and expensive. This problem can be solved by the use of rapid prototyping methodologies and associated CAD tools. In a previous paper we developed and...
A full-speed USB 2.0 device PHY IP chip is implemented in FPGA by using a Verilog synthesis. It works successfully to interface a NAND flash chip to PC. It consists of a clock generator, TX and RX. The TX and RX circuits include a NRZI encoder/decoder, a bit stuffer/unstuffer and a serializer/deserializer. The clock generator accepts a 60MHz clock and generates five 12MHz clock signals which are spaced...
The use of intrachip buses is no longer a consensus to build interconnection architectures for complex integrated circuits. Networks on chip (NoCs) are a choice in several real designs. However, the distributed nature of NoCs, the huge amount of wires and interfaces of large NoCs can make system/interconnection architecture debugging a nightmare. This work accelerates the NoC validation process using...
This paper presents the implementation of a configuration server for a SNTP synchronization platform which implements accurate synchronization solutions for Remote Terminal Units commonly used in industrial control processes. The configuration server provides settings to others platform devices using the BOOTP protocol and an interface that allow to administer the system. This environment requires...
Panchromatic Fourier Transform Spectrometer (PanFTS) is an Instrument Incubator Program (IIP) funded development to build and demonstrate a single instrument capable of meeting or exceeding the requirements of the Geostationary Coastal and Air Pollution Events (GEO-CAPE) mission. The PanFTS design provides atmospheric measurement capabilities in the IR and UV-Vis by using imaging FTS to provide full...
Specific to audio and video data multiplexing in Broadcast and TV system, a scheme of intellectual property module based on FPGA was advanced in this paper. After introduction to the related standards, the architecture of audio and video data multiplexing IP module and design processing were introduced. Through the experimental results, it is shown that the IP module could effectively multiplex audio...
We report on a Synchronous Ethernet based clock distribution and timestamp synchronization implementation over 1000BASE-T (Gigabit over twisted pair) Ethernet. A central 125 MHz global clock is distributed to all detector modules using only commercial off-the-shelf components. The timestamps generated on different modules has a maximum fixed offset of 24-60 ns (depending on the switch tested), and...
The theme for Autotestcon 2010 is “45 Years of Support Innovation - Moving Forward at the Speed of Light." This theme is particularly relevant for military ATE systems because it highlights the dichotomy of striving to maintain state-of-the-art testing capabilities, while at the same time needing to support legacy technologies that may be decades old - indeed, as old as Autotestcon itself. The...
SPI is one of the most commonly used serial protocols for both inter-chip and intra-chip low/medium speed data-stream transfers. In conformity with design-reuse methodology, this paper introduces high-quality SPI Master/Slave IPs that incorporate all necessary features required by modern ASIC/SoC applications. Based upon Motorola's SPI-bus specifications, version V03.06, release February 2003, the...
A firewall's complexity and processing time is known to increase with the size of its rule set. Empirical studies show that as the rule set grows larger, power consumption and delay time for processing IP Packets particularly on Hardware firewalls increases extremely, and, therefore the performance of the firewall decreases proportionally. This paper present a new FPGA (field programmable gate arrays)...
Modern Systems-on-Chip (SoC) development is moving toward multiprocessor-based design. Embedded systems have evolved from an uniprocessor to a multiprocessor approach, seeking better performance and less energy consumption. It is widely accepted that Multiprocessor Systems-on-Chip (MPSoC) will become the predominant class of embedded systems in future. In addition, advances in FPGA technology makes...
An Internet configurable distributed domotic network is presented. The network nodes are implemented with field programmable logic devices (FPGA). Each of them contains two modules, one for receiving field sensors activity signals and controlling devices responsible to modify the environment, and the other an ETHERNET compatible dedicated communication module. Simulation and implementation over SPARTAN...
An increasing number of Electronic Control Units in passenger cars and high communication traffic have led the car manufacturers to splitting a single CAN network into several dedicated sub-networks running concurrently. Test and evaluation tools for CAN based networks are available for years, but they are mostly focused on test scenarios with up to two CAN networks, often based on the standard CAN...
In this paper we describe a methodology to do rapid hardware prototyping of a part of a digital signal processing system described in Simulink. It explains the main technical problems when trying to go to hardware from a pure functional description and the solutions proposed to solve them. The methodology is applied on a proven model, from the architecture co-simulation, to the real hardware implementation...
The communication manager module embedded in a dedicated system configurable via Internet design description and XILINX Spartan 3 FPGA implementation are presented. Keeping Internet connectivity as a priority, minimum subsets of IEEE 802.3 standard rules for Ethernet data interchange and RFC826 and RFC791 recommendations for address resolution protocol (ARP) and Internet protocol (IP) respectively,...
Embedded system design is increasingly based on single chip multiprocessors because of the high performance and flexibility requirements. Contrary to desktop multi-core and usual multiprocessors, embedded multiprocessors are tightly constrained for the number of external DDR memories due to pin constraints which in turn may affect concurrency access for embedded parallel software implementation. In...
This paper proposed a RFID base-band transmission model based on the analysis of RFID base-band communication course, in which FPGA technology is employed to design a communication IP core, integrating functions of base-band encoding & decoding and data transmitting. The RTL design of base-band communication IP core based on modular method is also presented. The experimental studies based on Quartus...
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