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This paper presents a real-time Kvazaar HEVC intra encoder for 4K Ultra HD video streaming. The encoder is implemented on Nokia AirFrame Cloud Server featuring a 2.4 GHz dual 14-core Intel Xeon processor and Arria 10 PCI Express FPGA accelerator card. In our HW/SW partitioning scheme, the data-intensive Kvazaar coding tools including intra prediction, DCT, inverse DCT, quantization, and inverse quantization...
In recent years, there has been an increasing growth of using vision-based systems for tracking the players in team sports to evaluate and enhance their performance. Vision-based player tracking has high computational demands since it requires processing of a huge amount of video data based on the utilization of multiple cameras with high resolution and high frame rates. In this paper, we present...
In this demonstration, we develop a moving object extraction and classification system based on a heterogeneous acceleration platform that consists of a local Zynq terminal and FPGA clusters on the IBM SuperVessel cloud. Extraction of the moving object from the streaming video input is offloaded to the Zynq terminal, while the classification is executed on the cloud. FPGA high level synthesis and...
In many domains such as robotics and industrial automation, a growing number of Control Applications utilize cameras as a sensor. Such Visual Servoing Systems increasingly rely on Gigabit Ethernet (GigE) as a communication backbone and require real-time execution. The implementation on small, low-power embedded platforms suitable for the respective domain is challenging in terms of both computation...
In vision processing systems, many applications require multi-camera support. For the connection of the cameras to the processing system, multiple interfaces and a platform capable of handling sustained high data rates are essential. To cope with these requirements, a hardware-based solution using FPGA technology is advisable, especially when targeting space and energy constrained embedded systems...
A versatile display system VDS for advanced embedded systems is developed to unify and perform display operations, usually overloading the system's main processing unit in one hand and requiring more knowledge of display technologies in the other hand. In the presented approach, the developed display system should handle the well-known display functions optimally and should highly improve interactivity...
I/O data distribution for neighbourhood operations processed in parallel computing dominates the multimedia video processing domain. Hardware designers are confronted with the challenge of architecture obsolescence due to the lack of flexibility to adapt the I/O system while upgrading the parallelism level. The usage of reconfigurable computing solves the problem partially with the capability of hardware...
Recently introduced chips with ARM based processors and programmable logic provide huge potential for digital signal processing, networking and other applications. Many IP cores and operating systems have been prepared for these chips to simplify the development process. Nevertheless, the integration of IP cores and operating system is not covered by any development tool yet. Developers have to design,...
The reuse of predefined Intellectual Property (IP) can shorten development times and help the designer to meet time-to-market requirements for embedded systems. Using FPGA IP in a proper way can also mitigate the component obsolescence problem. System migration between devices is unavoidable, especially for long lifetime embedded systems, so IP portability becomes an important issue for system maintenance...
The System on Chip (SoC) can include Full High Definition (FHD) video processing, however the turn around time of algorithm improvement have been long. We provide the new method utilizing the behavioral synthesis. Therefore, the turn around time of the algorithm improvement and hardware implementation can be shorten.
Specific to audio and video data multiplexing in Broadcast and TV system, a scheme of intellectual property module based on FPGA was advanced in this paper. After introduction to the related standards, the architecture of audio and video data multiplexing IP module and design processing were introduced. Through the experimental results, it is shown that the IP module could effectively multiplex audio...
The theme for Autotestcon 2010 is “45 Years of Support Innovation - Moving Forward at the Speed of Light." This theme is particularly relevant for military ATE systems because it highlights the dichotomy of striving to maintain state-of-the-art testing capabilities, while at the same time needing to support legacy technologies that may be decades old - indeed, as old as Autotestcon itself. The...
Wireless video interphone cannot only provide portability, but also connect people through video communication, so it gains more and more interest in consumer electronics. To design such systems, it needs high performance video processing engine. In this paper, a Multi-processor system on a chip (MPSoC) is designed, in which there are one 32-bit RISC CPU and a low power, high performance H.264 codec...
We propose in this paper, a timing analysis of dynamic partial reconfiguration (PR) applied to a NoC (network on chip) structure inside a FPGA. In the context of a SDR (software defined radio) example, PR is used to dynamically reconfigure a baseband processing block of a 4G telecommunication chain running in real-time (data rates up to 100 Mbps). The results presented show the validity of our methodology...
We present a dynamic computing platform that allows for rapid prototyping of image and video processing applications systems. Here, an Ethernet MAC is used to stream video in and out of the FPGA. The output video is also sent to a video port for display. The system features a simple way to specify the dynamic video processing modules that are going to be multiplexed in time. The dynamic control is...
Specific to serial digital interface (SDI), this paper advanced a scheme of audio demultiplexing intellectual property module based on FPGA. After explaining the related standard protocols, the kernel architecture of audio demultiplexing IP module and design processing were introduced in detail. Finally, this paper gives an application of audio demultiplexing system based on IP module in SDI. It is...
An important share of the consumer electronics market is focused on devices capable of running multimedia applications, like audio and video decoders. In order to achieve the performance level demanded by these applications, it is important to develop specialized hardware IPs in order to cope with the most computational intensive parts. Nowadays, designers are facing the challenge of integrating several...
This paper discusses security requirements for self-reconfigurable consumer products build on commercially available programmable logic devices such as FPGAs. A secure reconfiguration controller (SeReCon) algorithm within embedded intellectual property (IP) core is presented which provides IP protection for self-reconfigurable systems. The SeReCon algorithm performs on-line verification of an IP core...
The OSSS methodology defines a seamless design flow for embedded HW/SW systems. It enables the effective use of high-level SystemCTM and C++ features like classes (object-oriented design paradigm), templates and method based communication for the description of SW and HW. Furthermore, it supports the OSCI SystemC Synthesis Subset for low-level HW description and HW IP integration. With Fossy we provide...
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