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FPGAs (Field Programmable Gate Arrays) are making their way into data centers (DC). They are used as accelerators to boost the compute power of individual server nodes and to improve the overall power efficiency. Meanwhile, DC infrastructures are being redesigned to pack ever more compute capacity into the same volume and power envelops. This redesign leads to the disaggregation of the server and...
■ Leverages Mali's scalable architecture ■ Scalable to 32 shader cores ■ Major shader core redesign ■ New scalar, clause-based ISA ■ New quad-based arithmetic units ■ New geometry data flow ■ Reduces memory bandwidth and footprint ■ Support for fine grain buffer sharing with the CPU
Detecting heavy activity aggregation in data streams is a critical task for many networking, data base and data-mining applications. The aggregation points often belong to hierarchical domains (e.g. IP domain, XML data tree, etc.). These aggregation points are referred to as hierarchical heavy hitters. The hierarchical domains is usually very large with respect to both the number of aggregation points...
FPGA capacity has grown rapidly and emerging large applications comprise a large number of hard and soft modules. The communication among these modules requires high demand from fabric interconnect, causing routing congestion and performance degradation. This problem will be more pronounced with process scaling since the technology is not improving wire resistance. A general technique to reduce interconnect...
FPGA is the first choice for developing the prototype system and the IP cores. Many existing network protocols are developed as IP cores, for example, the ethernet MAC open core. In this paper, an FPGA-based memory management system is proposed for the MAC protocol IP core, to facilitate the memory status acquisition and to support the functions in term of receiving packets from the upper layer, transmitting...
We present a hardware architecture of a heapsort algorithm, the sorting is employed in a subband coding block of a wavelet-based image coder termed Öktem image coder. Although this coder provides good image quality, the sorting is time consuming, and is application specific, as the sorting is repetitively used for different volume of data in the subband coding, thus a simple hardware implementation...
Embedded applications usually require Software/Hardware (SW/HW) designs to meet the hard timing constraints and the required design flexibility. Exhaustive exploration for SW/HW designs is a very time consuming task, while the adhoc approaches and the use of partially automatic tools usually lead to less efficient designs. To support a more efficient codesign process for FPGA platforms we propose...
Network router virtualization has recently gained much interest in the research community, as it allows multiple virtual router instances to run on a common physical router platform. The key metrics in designing network virtual routers are (1) number of supported virtual router instances, (2) total number of prefixes, and (3) ability to quickly update the virtual table. Existing merging algorithms...
We propose a combined length-infix pipelined search (CLIPS) architecture for high-performance IP lookup on FPGA. By performing binary search in prefix length, CLIPS can find the longest prefix match in (log L-c) phases, where L is the IP address length (32 for IPv4) and c>;0 is a small design constant (c=2 in our prototype design). Each CLIPS phase matches one or more input infixes of the same...
Memory efficiency with compact data structures for Internet Protocol (IP) lookup has recently regained much interest in the research community. In this paper, we revisit the classic trie-based approach for solving the longest prefix matching (LPM) problem used in IP lookup. In particular, we target our solutions for a class of large and sparsely-distributed routing tables, such as those potentially...
With the growing speed of computer networks, the core routers have to increase performance of longest prefix match (LPM) operation on IP address. While existing LPM algorithms are able to achieve high throughput for IPv4 addresses, the IPv6 processing speed is limited. In this paper we propose a new Hast-Tree Bitmap algorithm for fast longest prefix match for both IPv4 and IPv6 networks. The algorithm...
This paper presents the implementation of a configuration server for a SNTP synchronization platform which implements accurate synchronization solutions for Remote Terminal Units commonly used in industrial control processes. The configuration server provides settings to others platform devices using the BOOTP protocol and an interface that allow to administer the system. This environment requires...
Packet classification involving multiple fields is used in the area of network intrusion detection, as well as to provide quality of service and value-added network services. With the ever-increasing growth of the Internet and packet transfer rates, the number of rules needed to be handled simultaneously in support of these services has also increased. Field-Programmable Gate Arrays (FPGAs) provide...
The process of categorizing packets into flows in an Internet router is called packet classification. All packets belonging to the same flow obey a predefined rule and are processed in a similar manner by the router itself. For example, all packets with the same destination IP address and protocol may be defined as a flow. Packet classification is the foundation of many Internet functions such as...
Next generation Internet requires processing rich and flexible flow information in the network infrastructure. Rapid growth in network traffic results in major challenge to support flexible flow matching at line rate. Most of the existing work focuses on functionality rather than performance, and simply adopts either power-hungry TCAM or performance-in deterministic hashing. This paper exploits the...
Because of the rapid growth of both traffic and links capacity, the time budget to perform IP address lookup on a packet continues to decrease and lookup tables of routers unceasingly grow. Therefore, new lookup algorithms and new hardware platform are required to perform fast IP lookup. This paper presents a new scheme on top of the NetFPGA board which takes advantage of parallel queries made on...
Packet classification algorithms are widely used in network security devices. As network speeds are increasing, the demand for hardware acceleration of packet classification in FPGAs or ASICs is growing. Nowadays hardware architectures can achieve multigigabit speeds only at the cost of large data structures, which can not fit into the on-chip memory. We propose novel method how to reduce data structure...
It is becoming apparent that the next generation IP route lookup architecture needs to achieve speeds of 100-Gbps and beyond while supporting both IPv4 and IPv6 with fast real-time updates to accommodate ever-growing routing tables. Some of the proposed multibit-trie based schemes, such as Tree Bitmap, have been used in today's high-end routers. However, their large data structure often requires multiple...
Power consumption has become a limiting factor in next-generation routers. IP forwarding engines dominate the overall power dissipation in a router. Although SRAM-based pipeline architectures have recently been developed as a promising alternative to power-hungry TCAM-based solutions for high-throughput IP forwarding, it remains a challenge to achieve low power. This paper proposes several novel architecture-specific...
Lookup function in the IP routers has always been a topic of a great interest since it represents a potential bottleneck in improving Internet router's capacity. IP lookup stands for the search of the longest matching prefix in the lookup table for the given destination IP address. The lookup process must be fast in order to support increasing port bit-rates and the number of IP addresses. The lookup...
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