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This paper presents a real-time Kvazaar HEVC intra encoder for 4K Ultra HD video streaming. The encoder is implemented on Nokia AirFrame Cloud Server featuring a 2.4 GHz dual 14-core Intel Xeon processor and Arria 10 PCI Express FPGA accelerator card. In our HW/SW partitioning scheme, the data-intensive Kvazaar coding tools including intra prediction, DCT, inverse DCT, quantization, and inverse quantization...
The Kiwi project revolves around a compiler that converts C# .NET bytecode into Verilog RTL and/or SystemC. An alpha version of the Kiwi toolchain is now open source and a user community is growing. We will demonstrate an incremental approach to large system assembly of HLS and blackbox components, based on an extended IP-XACT intermediate representation. We show how to address multi-FPGA designs...
The number of IPs running concurrently on an FPGA has increased in recent years. Communication among these IPs has necessitated the introduction of the network on chip (NoC) for low-power, high-performance, and scalable on-chip networking. While NoCs are superior to traditional shared buses, there is an attendant resource overhead incurred by the NoC links, routers and network adapters. We present...
SpaceWire is a spacecraft on-board data-handling network which connects instruments to the mass-memory, data processors and control processors, which is already in orbit or being designed into more than 100 spacecraft. SpaceFibre is a new, multi-Gbits/s, on-board network technology, which runs over both electrical and fibre-optic cables. SpaceFibre is capable of fulfilling a wide range of spacecraft...
A SoC design of H.264 Video Encoding system is implemented based on FPGA in this paper. Intra prediction algorithm and baseline profile is selected, and H.264 encoder algorithm is designed as an IP core and embedded to the SoC through the interconnect interface AMBA AXI bus. The SoC is implemented on Xilinx Zynq-7000 FPGA and each functional module is simulated by Modelsim and tested within the SoC...
This paper presents a system that allows the secure remote configuration of an FPGA, which is assumed to be the only device in the secure zone. This means that no security critical information passes over the borders of the FPGA chip, reducing the opportunities for an attacker to break the system. In particular, bitstream compression in combination with partial reconfiguration is used to avoid the...
Specific to audio and video data multiplexing in Broadcast and TV system, a scheme of intellectual property module based on FPGA was advanced in this paper. After introduction to the related standards, the architecture of audio and video data multiplexing IP module and design processing were introduced. Through the experimental results, it is shown that the IP module could effectively multiplex audio...
This paper designs an RFID IP core by utilizing FPGA technology, which has advantages of internal task scheduling and high-speed encoding & decoding. The RTL design of base-band communication IP core based on modular method is presented. The RFID simulation model is established and the experiment results show that the proposed communication simulation model has a good performance, and the IP-core...
Internet Protocol Security (generally shortened to IPSec) is a framework of open standards that provides data confidentiality, data integrity, and data authentication between participating peers at the IP layer. The Data Encryption Standard(DES) is used to encrypt and decrypt packet data at IP layer; it turns clear text into cipher text via an encryption algorithm. The decryption algorithm on the...
Reuse of intellectual property (IP) of VLSI physical design facilitates integration of more components on a single chip in shrinking time-to-market. For intellectual property protection (IPP), various kinds of IP marks are embedded into the design for establishing the veracity of a legal owner. However, public verification of IP marks is not leakage-proof. Current techniques include a sufficiently...
Packet classification has been critical data path function for supporting quality of service (QoS), resource reservation protocol (RSVP) and broad range of multimedia services. Hardware based solution is necessary to keep up with high-speed rate up to OC192 processing. However, the range match in multi-fields classification is still one of the bottleneck problems. In this paper, a novel structure...
This paper proposed a RFID base-band transmission model based on the analysis of RFID base-band communication course, in which FPGA technology is employed to design a communication IP core, integrating functions of base-band encoding & decoding and data transmitting. The RTL design of base-band communication IP core based on modular method is also presented. The experimental studies based on Quartus...
The paper presents a novel WTB controller design method using SOPC (system on programmable chip) technology. The WTB Access IP (intellectual property), which is designed in Verilog HDL (hardware description language), achieves the function of encoding, decoding, FCS (frame check sequence) and bit stuffing. Finally the CPU and WTB controller are combined into one Alterapsilas Cyclone II EP2C8, so this...
The implementation of a recently proposed IP core of an efficient motion estimation co-processor is considered. Some significant functional improvements to the base architecture are proposed, as well as the presentation of a detailed description of the interfacing between the co-processor and the main processing unit of the video encoding system. Then, a performance analysis of two distinct implementations...
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