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Heterogeneous computing with hardware accelerators is a promising direction to overcome the power and performance walls in traditional computing systems. CPU-accelerator integrated architectures, such as CPU with ASIC or FPGA based accelerators, are able to provide customized processing according to application requirements and are thus particularly attractive to speed up computation-intensive applications...
The Low Frequency Aperture Array (LFAA) component of the Square Kilometer Array (SKA) involves the processing of 218 signal chains, which will be performed on custom FPGA boards, the Tile Processing Module (TPM). These TPMs, as well as firmware running on them, need to be managed, monitored and controlled by the rest of the system. This requires access to on-board devices and registers on running...
Power and energy profiling of multi-core embedded SoC designs is a daunting task due to the lack of fine grain accurate and high sampling rate monitoring infrastructures. Furthermore, shared components used in common by multiple processing cores, make these designs difficult to analyze consumption of concurrent threads. FPGA development boards are currently used to implement multi-core SoC prototypes...
Using Field Programmable Gate Arrays (FPGAs) as implementation platform for systems-on-chip (SoC) has become quite popular. Typically, the software part of the system functionality is executed on a soft-core processor. Debugging such systems becomes more difficult than standard SoCs since regular debugging facilities are not always available for the processor cores and also additional hardware problems...
Targeting the rapid development, with reduced complexity, of power converters control techniques, a field-programmable gate array (FPGA) based platform is proposed. The aim of the platform is to provide an effective support to the developer in the error-prone process associated to a traditional FPGA design flow. This work also enables remote hardware reconfiguration, and networking monitoring of power...
The design of spectrum monitoring receiver usually uses such a hardware model being consist of FPGA (Field Programmable Gate Arrays) and DSP (Digital Signal Processor) mainly, which requires the baseband datas and spectral datas under different bandwidths can be real-time transmitted between the FPGA and DSP. In this paper, according to the characteristics of the receiver, by using the ability, processing...
Intrusion detection approaches have been presented which detect anomalous malware behavior at runtime. Most techniques involve software-based analysis which is too slow to support the tight timing constraints often imposed on embedded systems. We propose a hardware-based intrusion detection approach which does not alter the functional performance of the system. When using a real-time operating system,...
Efficient use of FPGA resources requires FPGA-based performance models of complex hardware to implement one model cycle, i.e., one time-step of the original synchronous system, in several implementation cycles. Generally implementation cycles have no simple relationship with model cycles, and it is tricky to reconstruct the state of the synchronous system at the model-cycle boundaries if only implementation-cycle-level...
Hardware design with FPGAs can be a daunting task, even for experienced engineers. Even with sophisticated tools and improvements in high-level language to gates approaches, an engineer can expend significant effort simply implementing the design. Often, when the design is evaluated on the FPGA, the performance may not be what was expected. As a result, an engineer may go back and augment the design...
In the race towards computational efficiency, accelerators are achieving prominence. Among the different types, accelerators built using reconfigurable fabric, such as FPGAs, have a tremendous potential due to the ability to customize the hardware to the application. However, the lack of a standard design methodology hinders the adoption of such devices and makes the portability and reusability across...
Traditional approaches to evaluating a system's vulnerability to Single Event Upsets (SEUs) require elaborate and costly radiation beam testing or time-consuming simulation. While beam testing represents definitive evidence of a processor's susceptibility to radiation-induced upsets, we believe that low-cost in-house bit error injection tests provide a valuable tool both in their own right and as...
As FPGA resources continue to increase, FPGAs present attractive features to the High Performance Computing community. These include the power-efficient computation and application-specific acceleration benefits, as well as tighter integration between compute and I/O resources. This paper considers the ability of an FPGA to address another, increasingly important, feature - resiliency. Specifically,...
Optical Transport Networks (OTN) have emerged as a key enabler to increase the capacity of current telecommunication infrastructure. ITU-T Recommendation G.709 describes these networks by defining a flexible frame structure capable of carrying different client data signals. Recently, G.709 framer devices have received much attention from the telecommunication industry as next generation 10/40/100G...
This paper proposes Flex Core, a hybrid processor architecture where an on-chip reconfigurable fabric (FPGA) is tightly coupled with the main processing core. Flex Core provides an efficient platform that can support a broad range of run-time monitoring and bookkeeping techniques. Unlike using custom hardware, which is more efficient but often extremely difficult and expensive to incorporate into...
It is notoriously hard to verify and debug the final, board-level implementation of FPGA designs. The task involves manual intervention and creativity, unpredictable time costs, and it is further complicated by side-effects of the monitoring circuits inserted into the Design Under Test (DUT). In this paper, we introduce gNOSIS, an automated tool for board-level debugging and verification of FPGA designs...
This paper presents several test and monitoring techniques that have been deployed in some sub-systems of the CMS electromagnetic calorimeter readout electronics. The embedded online testability features of the Selective Readout Processor boards and of the endcap Trigger Concentrator Cards greatly simplified functional validation of the real-time hardware, facilitated development of automated production...
We have designed a local trigger board (LTB) for the Daya Bay Neutrino Experiment. To control and monitor the LTB, a VME bus based interface is implemented on the LTB. The control and status registers employed by the LTB can be accessed by this interface. This interface can also be used to read out the LTB data and update the LTB FPGA firmware. This interface has been tested and proved to be useful...
This paper presents one implementation of the Open Control Protocol (OCP) monitoring on the synthesized FPGA design using the implemented library of Synthesizable SystemVerilog Assertions (SSVA). The SSVA library is developed using the layer structure of SystemVerilog assertions. It is used in implementation of the monitors for two profiles of the OCP. SSVA library and OCP monitors are then functionally...
In this paper, a novel cellular nonlinear network emulator core which executes wave computing within an FPGA-based platform is proposed. This wave computer core has 4 ?? 4 parallel processing units and emulates 16, 384 nodes which are arranged in 128 ?? 128 normal grid form. The wave computer core can be programmed to generate active waves such as autowaves, travelling waves and spiral waves, and...
High-speed (10 Gb/s and above) network monitoring and traffic processing requires hardware acceleration. Different applications require different functions to be placed in hardware. Current packet capture cards include fixed firmware, which is difficult to extend. In this paper we propose an architecture for Modular Traffic Processing Platform (MTPP), which enables end users to easily modify hardware...
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