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It is notoriously hard to verify and debug the final, board-level implementation of FPGA designs. The task involves manual intervention and creativity, unpredictable time costs, and it is further complicated by side-effects of the monitoring circuits inserted into the Design Under Test (DUT). In this paper, we introduce gNOSIS, an automated tool for board-level debugging and verification of FPGA designs...
In this paper, we propose a novel rapid prototyping technique to produce a high quality CPU emulator at reduced development cost. Specification mining from published CPU manuals, automated code generation of both the emulator and its test vectors from the mined CPU specifications, and a hardware-oracle based test strategy all work together to close the gaps between specification analysis, development...
eBug is a debugging solution for software developed on the eMIPS dynamically-extensible processor. The off-chip portion of eBug is an application that performs tasks that would be too expensive or too inflexible to perform in hardware, such as implementing the communication protocols to interface to the client debuggers. The on-chip hardware portion of eBug is realized with a new approach: rather...
This paper describes the I/O subsystem of the eMIPS dynamically self-extensible processor. This processor, during execution, can load additional logic blocks that can perform a variety of functions from adding new instructions to the base instruction set to controlling I/O pins. A dynamically loaded logic block that acts as an I/O peripheral to software is what we term an Extensible I/O Peripheral...
Hardware compilation flows use a high-level language like C++ or Java and translate it directly to an HDL. In this paper we propose to split the problem in two; first use a regular compiler to do the front-end processing, then use the generated machine code to produce the HDL. The MIPS-to-Verilog (M2V) compiler translates blocks of MIPS machine code into a hardware design represented in Verilog. M2V...
This paper provides an overview of the I/O subsystem of the eMIPS dynamically self-extensible processor. During execution, eMIPS can load additional logic blocks that perform a variety of functions, from adding new instructions to the base instruction set to controlling I/O pins. A dynamically loaded logic block that acts as an I/O peripheral to software is what we term an extensible I/O peripheral,...
The PSL-to-Verilog (P2V) compiler can translate a set of assertions about a block-structured software program into a hardware design to be executed concurrently with the program. The assertions validate the correctness of the software program without altering the program's temporal behavior in any way, a result never previously achieved by any online model-checking system. Additionally, the techniques...
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