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This paper presents a reliable processor pipeline architecture resilient to multiple soft- and timing errors. It also presents a probabilistic quantification of its performance overheads. This reliable processor pipeline architecture has been implemented in the Leon3 VHDL open source processor. An FPGA prototype running under random fault injection has also been developed. This reliable processor...
Nowadays, computers are indispensable tools for most of everyday activities ranging from consumer electronics to industrial process automation. Complexity of new applications leads computer engineers to use embedded systems in order to develop high performance technological solutions that can achieve high speed processing while exploiting hardware resources efficiently. In order to develop embedded...
Reconfigurable Field Programmable Gate Arrays (FPGAs) are growing the attention of developers of mission- and safety-critical applications (e.g., aerospace ones), as they allow unprecedented levels of performance, which are making these devices particularly attractive as ASICs replacement, and as they offer the unique feature of in-the-field reconfiguration. However, the sensitivity of reconfigurable...
This paper presents an adaptable softcore chip multiprocessor (CMP). The processor instruction set architecture (ISA) is based on the VEX ISA. The issue-width of the processor can be adjusted at run-time (before an application starts). The processor has eight 2-issue cores that can run independently from each other. If not in use, each core can be taken to a lower power mode by gating off its source...
In this paper, we present the design and implementation of a BRAM-based multiported register file with arbitrary number of read and write ports. In order to avoid the conflicts associated with write ports, we present a register renaming technique that is applied between the compiler and the assembler. This technique enables the utilization of a banked-BRAM register file as a true multiported register...
This paper proposes Flex Core, a hybrid processor architecture where an on-chip reconfigurable fabric (FPGA) is tightly coupled with the main processing core. Flex Core provides an efficient platform that can support a broad range of run-time monitoring and bookkeeping techniques. Unlike using custom hardware, which is more efficient but often extremely difficult and expensive to incorporate into...
Modern processor architectures sacrifice timing predictability to improve average performance. Branch prediction, out-of-order execution, and multi-level cache hierarchies complicate accurate execution time estimates. The timing demands of Cyber Physical Systems (CPS) have led some to propose new processor architectures, including Precision Timed (PRET) processors, which simplify analysis of execution...
The paper presents a novel concept of processor aimed at symmetric-key cryptographic applications. Its architecture is optimized for implementation of common cryptography tasks. The processor has 128-bit separated data and key registers, dedicated instruction set optimized for key generation and management, embedded cipher, and embedded random number generator. From an architectural point of view,...
Side channel and fault injection attacks are a major threat to cryptographic applications of embedded systems. Best performances for these attacks are achieved by focusing sensors or injectors on the sensible parts of the application, by means of dedicated methods to localise them. Few methods have been proposed in the past, and all of them pinpoint the cryptoprocessor. However, when the cryptographic...
Soft processors often use data caches to reduce the gap between processor and main memory speeds. To achieve high efficiency, simple, blocking caches are used. Such caches are not appropriate for processor designs such as run ahead and out-of-order execution that require non-blocking caches to tolerate main memory latencies. Conventional non-blocking caches are expensive and slow on FPGAs as they...
Elliptic curve cryptography is a public key cryptosystem based on the elliptic curve discrete logarithm problem. The reason for the attractiveness of ECC is that there is no sub-exponential algorithm known to solve the elliptic curve discrete logarithm problem. This leads to lower memory requirements, lower computation requirements and higher security than other public key cryptosystems. This project...
The Instruction Set Architecure (ISA) of micro-processors is usually word oriented, so it is not optimized to perform bit level operations. A functional unit oriented to the bit manipulation could accelerate the computation increasing the microprocessor performance in terms of execution time. This work presents the experimental results of the integration between the Bit Manipulation Unit (BMU) described...
A multi-channel image superimposition system is designed in this paper. It can superimpose white-light image on infrared thermal image to generate mixture image. The system is realized on a FPGA chip and is mainly composed of multi-channel DMA controller and image superimposition module. Multi-channel DMA controller can realize data exchange between image superimpositon module and memory independent...
Modern embedded multiprocessors are complex systems that often require years to design and verify. A significant factor is that engineers must allocate a disproportionate share of their effort to ensure that modern FPGA chips architecture behave correctly. This paper proposes a design and creation of embedded multiprocessors architecture system focusing on its design area and performance. Embedded...
Asynchronous circuits possibly have several potential advantages in comparison with synchronous one. In this paper, we attempt to introduce asynchronous circuit design method into the control unit of our 8-bit microprocessor by the burst-mode design method and implemented the asynchronous 8-bit microprocessor with outputs to observe all registers and the program counter by using a standard FPGA development...
A 32-bit embedded Microprocessor based on the instruction set of ARMv4T architecture is designed and implemented in this paper. It adopts five-stage pipeline, implements separate instruction and data caches, contains memory management unit, and supports coprocessor instruction. This paper proposes perfect solution for the problem of data correlation, control correlation and resource correlation emerged...
Technological advances of Field Programmable Gate Array (FPGA) are making that this technology becomes the most preferred platform for the rapid prototyping of highly integrated digital systems. In addition, protection of processor-based systems to mitigate the harmful effects of radiation-induced upset events is gaining importance while technology shrinks. In this context, the main contribution of...
Rapid HDL is an object oriented software library for scripting the generation of synthesizable Verilog. A fully functional customized microprocessor is defined and automatically synthesized for an FPGA from an XML specification file. Using a library of blocks, a microprocessor fabric is defined in XML. Control states specify the connections between the fabric blocks during microprocessor operation...
This paper introduces the design method of CAN communication card based on the studies in depth of PCI technique and CAN protocols. The FPGA technique is used to design main controller of CAN communication card. The high reliability and high efficiency's logic control is make up based on state mechanism technique. The circular memory mechanism is used to design data buffer. The time-sharing of FPGA...
This Traditional UART IP hard core is poor at flexibility and transportability while UART IP soft core is only based on poll and interrupt mode at present which consumes so much time of CPU that the performance of embedded system is reduced greatly. UART IP soft core based on DMA mode is proposed and well elaborated using the characteristic of DMA. The IP core is AVALON bus-compatible with the control...
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