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This paper presents a reliable processor pipeline architecture resilient to multiple soft- and timing errors. It also presents a probabilistic quantification of its performance overheads. This reliable processor pipeline architecture has been implemented in the Leon3 VHDL open source processor. An FPGA prototype running under random fault injection has also been developed. This reliable processor...
Biologically-inspired machine vision algorithms - those that attempt to capture aspects of the computational architecture of the brain - have proven to be a promising class of algorithms for performing a variety of object and face recognition tasks. However these algorithms typically require a large number of arithmetic operations per image frame evaluated. Meanwhile, the increasing ubiquity of inexpensive...
Modern processor architectures sacrifice timing predictability to improve average performance. Branch prediction, out-of-order execution, and multi-level cache hierarchies complicate accurate execution time estimates. The timing demands of Cyber Physical Systems (CPS) have led some to propose new processor architectures, including Precision Timed (PRET) processors, which simplify analysis of execution...
Soft processors often use data caches to reduce the gap between processor and main memory speeds. To achieve high efficiency, simple, blocking caches are used. Such caches are not appropriate for processor designs such as run ahead and out-of-order execution that require non-blocking caches to tolerate main memory latencies. Conventional non-blocking caches are expensive and slow on FPGAs as they...
In this paper, a low-cost VLSI implementation of a pipeline fast Fourier transform (FFT) processor capable of supporting from 1k to 32k FFT sizes is presented. The radix-22/23 based pipeline structure reduces the steps of normal complex multiplications, and the single-path delay feedback (SDF) memory access method ensures a minimum (N-1) memory words to get the FFT results. As for the data-path in...
Modern embedded multiprocessors are complex systems that often require years to design and verify. A significant factor is that engineers must allocate a disproportionate share of their effort to ensure that modern FPGA chips architecture behave correctly. This paper proposes a design and creation of embedded multiprocessors architecture system focusing on its design area and performance. Embedded...
A 32-bit embedded Microprocessor based on the instruction set of ARMv4T architecture is designed and implemented in this paper. It adopts five-stage pipeline, implements separate instruction and data caches, contains memory management unit, and supports coprocessor instruction. This paper proposes perfect solution for the problem of data correlation, control correlation and resource correlation emerged...
This paper presents a modified pipeline single-path delay feedback (SDF) fast Fourier transform (FFT) architecture. The canonic signed digit (CSD) representation is used to design the function of complex multiplier, which is the main function block in the FFT processor. The processor of a 16-bit 16-point pipeline FFT is realized on the Xilinx Virtex-4 FPGAs. The achieved maximum clock frequency is...
In this paper a Globally-Asynchronous Locally-Synchronous (GALS) pipelined processor is implemented on synchronous commercial FPGAs. A simple pipelined accumulator-based processor is implemented as an example for a pipelined processor with varying stages' delays. A novel port controller is designed to ensure the proper operation of the pipeline under any distribution of stage delays. The results show...
Detailed architectural simulators suffer from a long development cycle and extremely long evaluation times. This longstanding problem is further exacerbated in the multi-core processor era. Existing solutions address the simulation problem by either sampling the simulated instruction stream or by mapping the simulation models on FPGAs; these approaches achieve substantial simulation speedups while...
It is important to develop a high-performance FFT processor to meet the requirements of real time and low cost in many different systems. So a radix-2 pipelined FFT processor based on field programmable gate array (FPGA) for wireless local area networks (WLAN) is proposed. Unlike being stored in the traditional ROM, the twiddle factors in our pipelined FFT processor can be accessed directly. A novel...
Power has become an important aspect in the design of general purpose processors. The conventional RISC processors consume too much power as compared with other processors. The power reduction in these processors is done in the fabrication step itself. But this is a complex process. If we can implement the techniques for power reduction in front end process then we can easily design the low power...
Rapid emergence of diverse wireless communication standards implies two crucial requirements on hardware mplementation: (1) Hardware platform flexibility for multistandard support, and (2) Rapid prototyping methodology for system validation under different use case scenarios. ASIP based platform, designed through architecture description language (ADL) fulfills both of these requirements in an elegant...
Field-programmable gate arrays (FPGAs) are increasingly being used for implementing embedded systems. Soft-core processors for FPGAs are also becoming popular due to reduced design costs and better flexibility. Commercial soft-core processors such as Altera Nios II and Xilinx Microblaze have been widely deployed. While some research has been done exploring the design space of soft-core CPUs, much...
Network processing devices in future, high-speed network nodes have to be capable of processing several hundred million packets per second. Additionally, they have to be easily adaptable to new processing tasks due to the introduction of new services or protocols. Field programmable gate arrays (FPGAs) and network processors are suitable devices fulfilling these requirements: The former offer configurability...
In this paper, the design for a dual core FFT processor based on CORDIC algorithm is presented. This design extracts the 2-base successions as the foundation, takes the FFT butterfly-shaped arithmetical unit as the object, uses the CORDIC algorithm superiority in the vector computation to simply the revolving factor calculation, and employs the assembly line technology to enhance the turnover rate...
We will explore how processing power of LEON3 processor can be enhanced by connecting small commercially available embedded FPGA (eFPGA) IP with the processor. We will analyze integration of eFPGA with LEON3 in two ways, inside the processor pipeline and as a co-processor. The enhanced processing power helps to reduce dynamic power consumption by Dynamic Frequency Scaling. More computational power...
This paper presents the design and implementation of a low power five-stage parallel pipelined structure of a MIPS-32 compatible CPU. The various blocks include the data-path, control logic, data and program memories. Hazard detection and data forwarding units have been included for efficient implementation of the pipeline. A modified architecture is proposed that leads to significant power reduction...
Multiprocessors on a chip are the reality of these days. Semiconductor industry has recognized this approach as the most efficient in order to exploit chip resources, but the success of this paradigm heavily relies on the efficiency and widespread diffusion of parallel software. Among the many techniques to express the parallelism of applications, this paper focuses on pipelining, a technique well...
The reconfigurable processors are the leading platforms being under consideration as a role model for reconfigurable computing systems. An application can be greatly accelerated by placing its computationally intensive portions of algorithms onto the reconfigurable platform. The gains are realized because the reconfigurable computing combines the benefits of both; the software and the ASIC solutions...
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