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A 32-bit embedded Microprocessor based on the instruction set of ARMv4T architecture is designed and implemented in this paper. It adopts five-stage pipeline, implements separate instruction and data caches, contains memory management unit, and supports coprocessor instruction. This paper proposes perfect solution for the problem of data correlation, control correlation and resource correlation emerged...
This paper presents a branch prediction algorithm and a 4-way set-associative cache for performance improvement of 32-bit RISC processor and a clock gating algorithm using ODC (observability don't care) operation for a low-power processor. The branch prediction algorithm has a structure using BTB (branch target buffer) and 4-way set associative cache using pseudo LRU (least recently used) algorithm...
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