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Modern processor architectures sacrifice timing predictability to improve average performance. Branch prediction, out-of-order execution, and multi-level cache hierarchies complicate accurate execution time estimates. The timing demands of Cyber Physical Systems (CPS) have led some to propose new processor architectures, including Precision Timed (PRET) processors, which simplify analysis of execution...
A prototype signal processing system of FPGA embedded multicore platform is presented to evaluate the performance and efficiency of signal processing on embedded multicore platform. The multicore processing algorithms of GSM and ADPCM are implemented. For the requirements in embedded applications, we point out the performance difference that come from the various processor core number and bus width,...
As chips have moved from homogeneous single core systems to much more complex, heterogeneous multi-core systems, the ability to create both uniform and efficient operating system services has begun to diminish. The importance of these services suggests that these primitives should no longer be virtual, but rather physical services built into modern computing devices. In this paper we outline some...
This paper describes instruction set extensions for a variant of multi-threading called micro-threading for the LEON3 SPARCv8 processor. We show an architecture of the developed processor and its key blocks - cache controller, register file, thread scheduler. The processor has been implemented in a Xilinx Virtex2Pro FPGA. The extensions are evaluated in terms of extra resources needed, and the overall...
High performance computing (HPC) has often benefited from special-purpose hardware. This paper examines the potential roles for several different approaches to hardware acceleration that are currently being deployed in HPC systems. Because each technology has different performance characteristics, as well as practical considerations (such as electrical consumption, physical interface, and cost), a...
Soft-core based multiprocessor systems are getting very popular in the FPGA design world. There are many computer architectures that has been used for building multiprocessor systems on FPGAs, including SMP (symmetric multiprocessor). One of the main drawback of this SMP systems is the unavailability of operating systems that allow programming multi-threaded applications that make good use of the...
As FPGA-based systems including soft-processors become increasingly common we are motivated to better understand the best way to scale the performance of such systems. In this paper we explore the organization of processors and caches connected to a single off-chip memory channel, for workloads composed of many independent threads. In particular we design and evaluate real FPGA-based processor, multithreaded...
Chip-multiprocessors are quickly becoming popular in embedded systems. However, the practical success of CMPs strongly depends on addressing the difficulty of multithreaded application development for such systems. Transactional memory (TM) promises to simplify concurrency management in multithreaded applications by allowing programmers to specify coarse-grain parallel tasks, while achieving performance...
We present a dynamic optimization technique, thread warping, that uses a single processor on a multiprocessor system to dynamically synthesize threads into custom accelerator circuits on FPGAs (field-programmable gate arrays). Building on dynamic synthesis for single-processor single-thread systems, known as warp processing, thread warping improves performances of multiprocessor systems by speeding...
The growth in size and performance of field programmable gate arrays (FPGAs) has compelled system-on-a-programmable-chip (SoPC) designers to use soft processors for controlling systems with large numbers of intellectual property (IP) blocks. Soft processors control IP blocks, which are accessed by the processor either as peripheral devices or/and by using custom instructions (CIs). In large systems,...
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