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Nowadays, computers are indispensable tools for most of everyday activities ranging from consumer electronics to industrial process automation. Complexity of new applications leads computer engineers to use embedded systems in order to develop high performance technological solutions that can achieve high speed processing while exploiting hardware resources efficiently. In order to develop embedded...
Reconfigurable Field Programmable Gate Arrays (FPGAs) are growing the attention of developers of mission- and safety-critical applications (e.g., aerospace ones), as they allow unprecedented levels of performance, which are making these devices particularly attractive as ASICs replacement, and as they offer the unique feature of in-the-field reconfiguration. However, the sensitivity of reconfigurable...
Evolutionary algorithms are another option for combinational synthesis because they allow for the generation of hardware structures that cannot be obtained with other techniques. This paper shows a parallel genetic programming (PGP) boolean synthesis implementation based on a low cost cluster of an embedded platform called SIE, based on a 32-bit processor and a Spartan-3 FPGA. Some tasks of the PGP...
This paper demonstrates the benefit of FPGAs for better power and energy efficiency when exploited for non-instruction fetch-based architecture. By replacing load/store architecture by non-instruction fetch-based designs for matrix multiplication, we reduced almost 100 percent of the dynamic power. Hence reconfigurable computing is the potential key to saving energy in battery-powered embedded systems...
Cache memory is a common structure in computer system and has an important role in microprocessor performance. A relationship between the performance of particular algorithm and main cache parameters such as associativity, number of words per block and cache size has been demonstrated. In this paper, we propose a reconfigurable cache with several working modes. The cache was physically implemented...
The paper presents a novel concept of processor aimed at symmetric-key cryptographic applications. Its architecture is optimized for implementation of common cryptography tasks. The processor has 128-bit separated data and key registers, dedicated instruction set optimized for key generation and management, embedded cipher, and embedded random number generator. From an architectural point of view,...
Side channel and fault injection attacks are a major threat to cryptographic applications of embedded systems. Best performances for these attacks are achieved by focusing sensors or injectors on the sensible parts of the application, by means of dedicated methods to localise them. Few methods have been proposed in the past, and all of them pinpoint the cryptoprocessor. However, when the cryptographic...
The Instruction Set Architecure (ISA) of micro-processors is usually word oriented, so it is not optimized to perform bit level operations. A functional unit oriented to the bit manipulation could accelerate the computation increasing the microprocessor performance in terms of execution time. This work presents the experimental results of the integration between the Bit Manipulation Unit (BMU) described...
The article presents a FPGA based novel embedded automobile data acquisition system, which records vehicle's, environment's and driver's operation information intuitively. The data acquisition system is useful in the fields of traffic accident analyze and accident responsibility confirmation. The core of system is Altera's Nios II processor in FPGA. According to the trigger conditions set by users,...
Modern embedded multiprocessors are complex systems that often require years to design and verify. A significant factor is that engineers must allocate a disproportionate share of their effort to ensure that modern FPGA chips architecture behave correctly. This paper proposes a design and creation of embedded multiprocessors architecture system focusing on its design area and performance. Embedded...
A 32-bit embedded Microprocessor based on the instruction set of ARMv4T architecture is designed and implemented in this paper. It adopts five-stage pipeline, implements separate instruction and data caches, contains memory management unit, and supports coprocessor instruction. This paper proposes perfect solution for the problem of data correlation, control correlation and resource correlation emerged...
In this paper, a method of design a kind of wireless order system is put forword, sepecially for noshery. Upper machine (the cashier desk) and lower machine (terminal equipment) are included in the system, those will be designed separately because of different function but the design of the terminal equipment is the emphasis. The system use FPGA as control and logic core to cooperate with many peripherals...
Our previous study has shown the potential of using a computer system to accurately decode electromyographic (EMG) signals for neural controlled artificial legs. Because of computation complexity of the training algorithm coupled with real time requirement of controlling artificial legs, traditional embedded systems generally cannot be directly applied to the system. This paper presents a new design...
This work presents the design methodology and the optimal FPGA implementation of a hardware video interface that can be used in any embedded system with microprocessors or microcontrollers for direct connection to a VGA compatible monitor. The design level is lowered to schematic details, which offers more optimization possibilities than any hardware description language. Such a visual design was...
Artificial Neural Networks (ANN) are used to perform tasks like classification, pattern recognition and function approximations in many cases to which traditional approaches are not well suited. Hardware implementations have been presented, mainly in academical works, in order to take advantage of the inherent parallelism in ANNs. In the field of embedded systems it is desirable to have faster and...
We propose a performance estimation technique for a multi-core segmented bus platform, SegBus. The technique enables us to assess the performance aspects of any specific application on a particular platform configuration, modeled in Unified Modeling Language (UML). We present methods to transform Packet Synchronous Data Flow (PSDF) and Platform Specific Model (PSM) models of the application into Extensible...
This paper introduces the working principle of space vector pulse width modulation (SVPWM), and presents a new circuit realization of SVPWM generator based on FPGA-embedded technique. MicroBlaze is a 32-bit high-performance processor embedding in the FPGA chip, and the left logical units can be used to design IP cores that needed, thus software and hardware can be combined to realize this SVPWM control...
Technological advances of Field Programmable Gate Array (FPGA) are making that this technology becomes the most preferred platform for the rapid prototyping of highly integrated digital systems. In addition, protection of processor-based systems to mitigate the harmful effects of radiation-induced upset events is gaining importance while technology shrinks. In this context, the main contribution of...
This Traditional UART IP hard core is poor at flexibility and transportability while UART IP soft core is only based on poll and interrupt mode at present which consumes so much time of CPU that the performance of embedded system is reduced greatly. UART IP soft core based on DMA mode is proposed and well elaborated using the characteristic of DMA. The IP core is AVALON bus-compatible with the control...
This paper introduces a high speed data acquisition system based on NIOS II, especially focuses on the development process of NIOS II soft-core in data acquisition system. Acquisition data is transferred to computer for displaying and analysising by USB interface. Acquisition rate is 250MSPS, the real-time and low-pass filter is used as well, the acquisition data is stored in the RAM first, then processed...
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