The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
To improve the speed of the image processing chip, to quick share the market and to reduce costs, this paper designs a chip with Harvard Architecture and FPGA. The chip is also used with a new hardware algorithm. Using the chip, the processing time is 13.2% less than the time of the chip with Von Neumann Architecture. The used units of filter are 13% of the whole FPGA gates, less than the claim part...
Cache memory is a common structure in computer system and has an important role in microprocessor performance. A relationship between the performance of particular algorithm and main cache parameters such as associativity, number of words per block and cache size has been demonstrated. In this paper, we propose a reconfigurable cache with several working modes. The cache was physically implemented...
In this paper, a low-cost VLSI implementation of a pipeline fast Fourier transform (FFT) processor capable of supporting from 1k to 32k FFT sizes is presented. The radix-22/23 based pipeline structure reduces the steps of normal complex multiplications, and the single-path delay feedback (SDF) memory access method ensures a minimum (N-1) memory words to get the FFT results. As for the data-path in...
A multi-channel image superimposition system is designed in this paper. It can superimpose white-light image on infrared thermal image to generate mixture image. The system is realized on a FPGA chip and is mainly composed of multi-channel DMA controller and image superimposition module. Multi-channel DMA controller can realize data exchange between image superimpositon module and memory independent...
In this paper, design of a length variable FFT processor is presented. Mixed radix algorithm is adopted which mixes radix-2, radix-22 and radix-2/4/8 algorithms to handle 2n point, 4n point and 8n point FFT, and SDF architecture is used. By connecting or bypassing specific processing elements, the processor can be configured as 8192 point, 4096 point, 2048 point and 1024 point FFT processor. To improve...
Our previous study has shown the potential of using a computer system to accurately decode electromyographic (EMG) signals for neural controlled artificial legs. Because of computation complexity of the training algorithm coupled with real time requirement of controlling artificial legs, traditional embedded systems generally cannot be directly applied to the system. This paper presents a new design...
A prototype signal processing system of FPGA embedded multicore platform is presented to evaluate the performance and efficiency of signal processing on embedded multicore platform. The multicore processing algorithms of GSM and ADPCM are implemented. For the requirements in embedded applications, we point out the performance difference that come from the various processor core number and bus width,...
In the downlink module of Orthogonal Frequency Division Multiple Access (OFDMA) system, there is needed an alterable points FFT processor. Therefore, it is meaningful to design a FFT processor for the FFT processor which input data points could be alterable. In this paper the variable input FFT processor is designed to meet the requirements of OFDMA system. For this, in this paper we select the 2D...
Networks-on-Chip (NoCs) for future many-core processor platforms integrate more and more heterogeneous components of different types and many real-time and latency-sensitive applications can run on a single chip concurrently. The reconfigurable FPGA and reconfigurable NoCs have emerged for the purpose of reusability. Those types' traffics within NoCs exhibit diverse, burst, and unpredictable communication...
It is important to develop a high-performance FFT processor to meet the requirements of real time and low cost in many different systems. So a radix-2 pipelined FFT processor based on field programmable gate array (FPGA) for wireless local area networks (WLAN) is proposed. Unlike being stored in the traditional ROM, the twiddle factors in our pipelined FFT processor can be accessed directly. A novel...
Modern advancements in configurable hardware, most notably field-programmable gate arrays (FPGAs) have provided an exciting opportunity to discover the parallel nature of modern image processing algorithms. On the other hand, PlayStation3 (PS3) game consoles contain a multi-core heterogeneous processor known as the cell, which is designed to perform complex image processing algorithms at a high-performance...
This paper presents the realization of the forward automatic censored cell averaging detector (F-ACCAD), a novel CFAR algorithm for detecting targets in log-normal distribution clutter recently published . The algorithm is realized through an FPGA-based parallel architecture. The timing constraints of high resolution radar applications are considered and satisfied in the system. The sequential nature...
In this paper, a novel control generation methodology based on the Polytope Model is proposed for the QR decomposition problem mapped onto systolic array processors. Many FPGA accelerator implementations for QR decomposition based on array of processors have been studied. However, the design of the control path is one of the greatest challenges in the design of complex signal processing applications...
This paper proposes a digital scene simulator system for point target detecting and tracking. The hardware platform mainly consists of FPGA and DSP, which are grouped together in an efficient way. And a target detecting and tracking algorithm is proposed and implemented in the platform. Experimental results show that proposed system can simulate deep out space scene and test an algorithm that is efficient...
The FPGA-based high throughput 128 bits AES cipher processor is proposed in this paper. We present an equivalent pipelined AES architecture working on CTR mode to provide the highest throughput up to date through inserting some registers in appropriate points making the delay shortest, when implementing the byte transformation in one clock period. The equivalent pipelined architecture does not change...
In this paper, a generic elliptic curve (EC) arithmetic unit with high flexibility and small chip covered area is proposed. This EC arithmetic unit is based on the one dimensional systolic architectural realization of a proposed modified multiplication - inversion algorithm that through appropriate initialization uses the algorithmic structure of inversion to also perform multiplication. The proposed...
In popular symmetric ciphers, S-box substitution is the core operation that dominates executions of cryptographic algorithms. In this paper, a method of application-specific instruction-set extension is used for accelerating the key operation in symmetric cryptography. Two instructions for S-box access are designed by constructing a novel flexible on-chip parallel substitution box unit that consists...
In this paper, the design for a dual core FFT processor based on CORDIC algorithm is presented. This design extracts the 2-base successions as the foundation, takes the FFT butterfly-shaped arithmetical unit as the object, uses the CORDIC algorithm superiority in the vector computation to simply the revolving factor calculation, and employs the assembly line technology to enhance the turnover rate...
Filtering data in real-time requires dedicated hardware to meet demanding time requirements. If the statistics of the signal are not known, then adaptive filtering algorithms can be implemented to estimate the signals statistics iteratively. Modern field programmable gate arrays (FPGAs) include the resources needed to design efficient filtering structures. This paper aims to combine efficient filter...
An optimized algorithm using neural network is presented, and the characteristics of neural network are introduced. This algorithm has advantages in increasing precision, reducing calculating time, reducing additional memory and the deterioration of the harmonic. This paper introduces a new FPGA: ALTERApsilaS ACEX chip and EDA tool: MAX+PLUS II. For recent years, FPGA is increasingly developing very...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.