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Nowadays, computers are indispensable tools for most of everyday activities ranging from consumer electronics to industrial process automation. Complexity of new applications leads computer engineers to use embedded systems in order to develop high performance technological solutions that can achieve high speed processing while exploiting hardware resources efficiently. In order to develop embedded...
This paper presents dynamic reconfiguration of a register file of a Very Long Instruction Word (VLIW) processor implemented on an FPGA. We developed an open-source reconfigurable and parameterizable VLIW processor core based on the VLIW Example (VEX) Instruction Set Architecture (ISA), capable of supporting reconfigurable operations as well. The VEX architecture supports up to 64 multiported shared...
This paper describes a hardware demonstrator for wireless communication applications which is integrated into a single FPGA. The physical layer (PHY) is based on the Orthogonal Frequency Division Multiplexing (OFDM) transmission technique and is implemented with dedicated logic. The data link layer is defined by program code which is executed on the LEON3, a RISC processor module which is based on...
Wireless sensor nodes are essential elements in wireless sensor networks. There are two important issues which need to be considered in order to build a sensor node: low power consumption and scalability. This paper proposes and presents a SoC architecture of wireless sensor node based on open source IP blocks such as OpenRISC 1200 microprocessor core and Wishbone Interconnect Matrix bus core. This...
Nios II is the soft-core 32 bits RISC processor of the Altera Corporation which can be implied in its FPGA. Users can design their own peripherals accord with Avalon Bus specification in Nios II system. A new design method for plus width module (PWM) peripheral is presented, which is completed by Verilog HDL. Comparing to the common PWM module, this new PWM module use the hardware units (logic elements...
New media and signal processing applications demand ever higher performance while operating within the tight power constraints of mobile devices. A range of hardware implementations is available to deliver computation with varying degrees of area and power efficiency, from general-purpose processors to application-specific integrated circuits (ASICs). The tradeoff of moving towards more efficient...
This paper explores the advantages of adding an MMX extension to the MicroBlaze (MB) soft processor,through its FSL ports. The implemented MMX unit is described in detail, were emphasis has been done in parallelizing the instruction execution. The propagation delays and FPGA resources consumed obtained for the different blocks during the synthesis phase for a Virtex-II target device are also shown...
The design and verification of a 32-bit general- purpose microprocessor, which is compatible with ARM? RISC core, is described. In the architectural point of view, the processor has 3-stage pipeline, 6 register banks, 32-bit ALU, and 4-cycle MAC. The core described here was designed by latch base for low power and low complexity. Its functional operation was verified by comparison the results of logic...
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