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Excessive IR-drop during scan shift can cause localized IR-drop around clock buffers and introduce dynamic clock skew. Excessive clock skew at neighboring scan flip-flops results in hold or setup timing violations corrupting test stimuli or test responses during shifting. We introduce a new method to assess the risk of such test data corruption at each scan cycle and flip-flop. The most likely cases...
Detailed knowledge of a circuit’s timing is essential for performance optimization, timing closure, and generation of test patterns to detect small-delay defects. When an input transition is applied to the circuit’s inputs, the resulting delay is not only determined by the propagation path, but also influenced by the power-supply noise. We introduce a path-sensitization procedure which precisely controls...
The influence of technological and circuit parameters variations on the combinational circuit elements delay increases with the transistor size reduction. Delay uncertainty comes from the parameter values dispersion; therefore, it is critical to analyze the possible delay variance. This paper presents the solution to problems of complex digital circuits performance analysis with the presence of the...
This paper presents design of wide fan-in gate for low power and high speed operations with reduced transistor count. In this work some circuital modifications are done to reduce the number of stacked transistor between input and output hence reducing the delay of the designed wide fan-in OR-gate. Also the average power dissipation of the circuit is reduced as it has less number of switching nodes...
Thomson coil actuators (also known as repulsion coil actuators) are well suited for vacuum circuit breakers when fast operation is desired such as for hybrid AC and DC circuit breaker applications. This paper presents investigations on how the actuator drive circuit configurations as well as their discharging pulse patterns affect the magnetic force and therefore the acceleration, as well as the mechanical...
This paper explores the models of the energy-optimal voltage (VOPT) of near/sub-threshold digital VLSI circuits with a focus on the support for a wide range of nodal switching rates. The previous models can estimate the VOPT of the circuits having relatively high nodal switching rates (VOPT, H), but can become inaccurate in finding the VOPT of the circuits having low nodal switching rate. In this...
Gate-level power estimation based on foundry-supplied standard cell libraries is a common analysis step during digital design. Surprisingly little is known about the accuracy of this approach and the suitability for different circuit types. At the same time, commercial tools implementing this approach are employed broadly and often regarded as the reference when comparing estimation methodologies...
Multiple Dynamic Supply Voltage (MDSV) is an attractive way to reduce dynamic power in Integrated Circuits. This technique introduces Level Shifter (LS) in order to commute from one voltage domain to another. Nevertheless, some LS inserted during the physical synthesis can degrade performance and power consumption, especially in specific power modes. In this work, we present a novel approach to dynamically...
In this paper we propose a new structure for NMOS based leakage feedback approach. The new proposed circuit technique includes NMOS only sleep transistors in parallel to both pull-up and pull-down paths which will reduce subthreshold current while saving the exact logic state. Based on 45nm Berkeley predictive technology model (BSIM 4), post layout simulation on microwind shows that as compared to...
In this paper, we present COFFE (Circuit Optimization For FPGA Exploration), a new fully-automated transistor sizing tool for FPGAs. Automated transistor-level CAD tools are an important part of the architecture exploration flow because they provide accurate area and delay estimates of low-level FPGA circuitry, which must be obtained for each architecture. We show that modeling transistors as linear...
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