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Field Programmable Gate Arrays (FPGA) are flexible, so they are commonly used in many high speed applications. However, power constraints are the most important limiting factors while implementing high speed adaptable applications. This work addresses the optimization of the execution time and power consumption. We propose a new design methodology by extending Algorithm-Architecture-Adequacy (AAA)...
Image compression is one of the key image processing techniques in signal processing and communication systems. Compression of images leads to reduction of storage space and reduces transmission bandwidth and hence also the cost. Advances in VLSI technology are rapidly changing the technological needs of common man. One of the major technological domains that are directly related to mankind is image...
An FPGA-based prototype of a custom high-performance network hardware has been implemented, integrating both a switch and a network interface in one FPGA. The network interfaces to the host processor over HyperTransport. About 85% of the slices of a Virtex IV FX100 FPGA are occupied and 10 individual clock domains are used. Six of the MGT-blocks of the device implement high-speed links to other nodes...
A hardware design for genetic algorithm (GA) can implement only one specific cost function of a problem at a time. Actually, different GA applications require different GA hardware architecture. The development of a flexible very-large-scale integration (VLSI) for GA has been proposed in this paper. For the hardware architecture, we has develop on a random number generator (RNG), crossover, and mutation...
The sequential minimal optimization (SMO) algorithm has been widely used for training the support vector machine (SVM). In this paper, we present the first chip design for sequential minimal optimization. This chip is implemented as an intellectual property (IP) core, suitable to be utilized in an SVM-based recognition system on a chip. The proposed SMO chip has been tested to be fully functional,...
In this paper a methodology of symbolic RTL synthesis, for circuits implemented in FPGA devices, is presented. First, symbolic functions are separated from binary and arithmetic ones. Next, the multi-valued logic network is optimized using our methods of symbolic functional decomposition, designed for functions with multi-valued inputs and multi-valued outputs. Finally, the whole circuit is implemented...
A new approach to the functional decomposition based on the theoretical-set method of q-partition numerical conjuncterms and an introduced concept of decomposition clones of different given forms of Boolean functions of n variables has been considered. The theorem about disjoint compatible decomposition of functions system has been formulated. The suggested algorithm is illustrated by examples.
Continuous transistor scaling due to improvements in CMOS devices and manufacturing technologies is increasing processor power densities and temperatures; thus, creating challenges when trying to maintain manufacturing yield rates and devices which will be reliable throughout their lifetime. New microarchitectures require new reliability-aware design methods that can face these challenges without...
Run-time reconfigurable computing extends the classic role of FPGAs towards processing elements which feature multitasking similar to a micro processor. The main advantage of this usage is based on the granularity of the reprogrammable device which can be optimally adapted to each task that has to be executed. Hence, scheduling for such a usage scenario becomes apparent, where a set of tasks with...
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