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This paper presents the design of high performance co-processor used to calculate the posterior probabilities for the embedded speech recognition of CHMM (Continuous Hidden Markov Model) with the MPIE (Maximum Probability Increase Estimation) algorithm to finish the most computation intensive operations in the speech recognition flow. The design of the co-processor is verified on Xilinx FPGA platform...
In order to detect the target position real-timely,a real time target detecting system based on tms320F2812 DSP and Spartan3-SC3S400 FPGA is designed.The design,hardware structure,a target detecting method and software char flow of FPGA and DSP are presented.The system is tested by a 1K×1K image,the processing time is 1.3ms, experiments results show that the method is feasible,the simple design and...
In view of the large and high real-time data transmission in the current strapdown INS, USB interface was integrated into the strapdown INS, and a strapdown inertial navigation real-time data processing system composed of the DSP, FPGA and the USB interface was designed. The system composition and working principle were described; the overall hardware design and software design of the system were...
We propose a new way to save energy in adaptive processors. According to an execution context the custom instruction set of an adaptive processor is selectively 'muted' at run time and thus the energy efficiency is significantly increased. Implemented are multiple so-called 'muting modes' each leading to particular leakage energy savings. A key challenge of this work is to determine which of the muting...
Following the synthesis and expansion of airborne devices' functions and the requirement of miniaturization of size, the traditional analog IF signal receiving system shows large size, high power consummation and low stability. It is difficult to satisfy the requirement of modern communications. This system applies software radio design thought and implements all digital IF signal processing and 485...
In this paper, a color image fusion system based on DSP and FPGA is introduced. In the system, TMS320DM642 is used as the kernel processor to finish the image's fusion arithmetic, storage and display. FPGA, which has the ability to control the logic of image capturing, is used as the assistive processor. The experiment shows that this technology can obtain color fusion image.
This article proposes a hardware triply selective Rayleigh fading channel emulator which is implemented by incorporating spatial and inter-tap correlation matrices into uncorrelated frequency-flat Rayleigh fading waveforms with a Kronecker product method. The Kronecker product of square roots of three correlation matrices are computed in real time via serial, parallel, or mixed serial-parallel computational...
A novel rank order statistic calculation algorithm for OS CFAR is presented. OS CFAR gives improved performance in a multitarget environment as compared to CA CFAR. However, the computational requirements of sorting data arrays complicate its implementation. We present an algorithm to overcome this challenge by employing a rank order statistic finding algorithm coupled with the exploitation of parallelism...
Application Specific Instruction-set Processors (ASIPs) are needed to handle the future demand of flexible yet high performance computation in mobile devices. The flexibility of ASIPs makes them preferable over fixed function Application Specific Integrated Circuits (ASICs). Also, a well designed ASIP, has a power consumption comparable to ASICs. However the cost associated with ASlP design is a limiting...
Nowadays, long-distance data transmission is one of the key features for remote sensing systems such as seismic exploration. In these kinds of systems, ordinary twisted pair is more suitable than fiber optics because of working environments or limited costs. But there are two limitations as long distance and data transmission speed which are not easy to be improved in these systems. We designed and...
A hardware/software co-simulator has been developed for a video processing SOC. The simulator is composed of a PC and a FPGA board. The simulator realizes seamless connection between software on a PC and hardware circuits in a FPGA chip. Therefore, partial VLSI design is possible within the software. As modification on both software system and FPGA circuits are easy and as the simulation speed is...
A robot vision system is developed based on an intelligent image gathering card that contains an FPGA (Field Programmable Gate Array) and a DSP (Digital Signal Processor) as main calculators. Two real-time visual modules are developed through the cooperation of hardware logics on FPGA and software on DSP. First, with edge images extracted by the FPGA, a highly efficient algorithm is designed to extract...
Xilinx and Mathworks jointly proposed System Generator (SysGen) and Simulink to accelerate development of DSP (digital signal processing) style applications on Field Programmable Gate Array (FPGA) chips. However, most of developments with Simulink and SysGen end at simulation stage without complete stand-alone implementation on FPGA since these tools do not come up with sufficient IO system libraries...
The design and implementation of a higher order Moving Target Indication (MTI) engine is presented. This is part of a single chip radar signal processor also incorporating the subsequent algorithms. The bottleneck in use of higher order filters for MTI is not an algorithmic one but one related to implementation. Thus the challenge is to minimize area utilization and achieve the required speed. The...
This paper presents a short state-of-the-art Field Programmable Gate Array (FPGA) technology. An efficient design methodology for designing FPGA-based controllers is also described. To illustrate the interest of this methodology, a complex sensorless algorithm for AC drives has been chosen. It consists in an Extended Kalman Filter (EKF), which is most of the time implemented in a DSP controller. In...
In this paper, a dedicated edge detection processor architecture based on field programmable gate arrays is presented. The architecture is an optimization of the Sobel edge detection filter, specifically focusing on the reduction of the computation time. The proposed architecture reduces the number of calculations required for the edge detection process by enhancing the data reuse, i.e. minimizing...
Iris Identification is nowadays one of the most promising techniques in Authentication. Most modern iris recognition systems are currently deployed on traditional sequential digital systems, such as a simple DSPs or MIPS processor. However, in this method, we can only match each data one by one, which will waste much time. In this study, iris matching, a repeatedly executed portion of a modern iris...
Fast Fourier transform (FFT) is an essential component in many digital signal processing and communications systems. The performance of the FFT component is a key factor in evaluating the overall system performance, and it is common to use it as a benchmark for the whole system. Many attempts have been made to enhance the FFT performance, both on algorithm and implementation levels. Software and hardware...
Digital cameras have been a popular candidate device employed in visual sensing applications. Its attractive features, including wide detection range, high resolution, and reliable performance, have made the digital camera an indispensable sensor in surveillance and machine vision systems. In this paper, we propose an implementation of real-time motion detection using a fully digital integrated circuit...
To meet the complex requirements of the miniature embedded integrated (INS/GPS) navigation system based on DSP, all peripheral circuits were integrated in single chip of FPGA, such as logic control module, serial/parallel data conversion and FIFO(First In First Out), etc. The multi-channel UART(Universal Asynchronous Receiver Transmitter) consists of the data conversion circuit and FIFO. In addition,...
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