The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
This paper describes a new methodology of construction of the internal activity block of an ICEM-CE model of an FPGA based on a predictive approach using the estimation tools of the dynamic power and the static timing proposed by the manufacturer of the integrated circuit.
In this work, we designed a Visitor Counting Machine (VCM) in terms of power efficient circuit using family of three different IO Standards which are LVTTL, Mobile DDR, HSUL 12. These three different IO Standards are compared with each other on the basis of Clock power, Logic power, Signal power, IOs, Leakage power and Total power consumption to search the most power efficient one. In order to find...
Hardware Trojan Threats (HTTs) are stealthy components embedded inside integrated circuits (ICs) with an intention to attack and cripple the IC similar to viruses infecting the human body. Previous efforts have focused essentially on systems being compromised using HTTs and the effectiveness of physical parameters including power consumption, timing variation and utilization for detecting HTTs. We...
Network traffic keeps increasing like as the demand of video streaming. Routers and switches in wire-line networks require guaranteed line rate as high as 20Gbp/s as well as advanced quality of service (QoS). Hybrid SRAM and DRAM architecture previously presented with the benefit of high-speed and high-density requires complex memory management. As a result it, it has hardly supported large numbers...
Side Channel Analysis (SCA) is a powerful class of attacks to extract cryptographic keys used in a wide variety of electronic devices that involves authentication, digital signatures or secure storage. Cryptographic systems are made up of cryptographic primitives implemented in Complementary Metal-Oxide-Semiconductor technology. But CMOS logic gates are designed to minimize their energy usage when...
As technology scales, leakage power shares a dominant part in the total power dissipation of the chip and reaches up to 50% or even higher at elevated temperatures in 45 nm technology. Leakage power dissipation is especially problematic for FPGAs due to their reconfigurable nature and large number of inactive resources. Body biasing is an efficient technique to reduce leakage current which has been...
Energy harvesting systems are becoming more attractive for remote sensing applications. In this paper, we propose a new technique that performs the voltage scaling in conjunction with frequency scaling to achieve ultra low power design in ASIC/FPGA. To detect errors and obtain the corrected data without any loss in performance, a delayed clock flip-flop is utilized to borrow timing from non-critical...
Usage of multiple supply voltages has raised new design challenges in IC design. We focus on the problem of power aware placement when dual supply voltages provide two high performance and low power working modes on each FPGA tile. To meet timing constrains, all logic elements within a tile need to work in the high performance mode when at least one element within that tile has tight timing requirements...
Side channel attacks are known to be efficient techniques to retrieve secret data. In this context, this paper concerns the evaluation of the robustness of triple rail logic against power and electromagnetic analyses on FPGA devices. More precisely, it aims at demonstrating that the basic concepts behind triple rail logic are valid and may provide interesting design guidelines to get DPA resistant...
This paper presents an experimental evaluation on the feasibility of using an adaptive clock to enhance the performance of a Fast Fourier Transform (FFT). The FFT is implemented on an FPGA and results are simulated using commercial EDA tools. Dynamic power consumption and processing speed are compared to a standard FFT implementation using a fixed clock. Results show that using a dynamically variable...
According to the specified standard of airborne Photogrammetry, digital airborne cameras must have higher performance than ordinary civil cameras, which must shoot with shorter time interval and will generate huge data stream. In this paper, a digital airborne camera is designed and implemented in a single FPGA chip as a SOPC approach. The functions of image acquisition, storage and display are implemented...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.