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Streaming processing is an important technology that finds applications in networking, multimedia, signal processing, etc. However, it is very challenging to design and implement streaming applications as they impose complex constraints. First, the tasks involved in the streaming applications must complete the computation under a latency constraint. Second, streaming systems are built under more and...
In the workflow of SKA-SDP (Square Kilometer Array Radio Telescope-Scientific Data Processing), FFT (Fast Fourier Transform) calculation takes a significant proportion of computation overhead. Moreover, FFT computation has to be done within the tight power budget, which existing generic high performance computing architectures cannot meet. To explore power efficiency of FFT computation, this study...
Throughput, area and power optimized designs for the advanced encryption standard algorithm are proposed in this paper. The presented designs are suitable for the encrypt-only AES-128 algorithm. Both designs integrate pipelining and iterative architectures in one design. This is achieved through applying the concept of partial loop unrolling where iterations and multistage pipelining are used to optimize...
One of the most important topics of today is a packet processing in data centers with respect to the power consumption and efficient utilization of computational resources. The ARM architecture has proved to be an energy efficient computational system. Together with an integrated FPGA on a single die, it offers potentially a high performance with respect to the power consumption. DPDK - a set of libraries...
Due to the ever increased energy consumption, large research effort has devoted to the energy efficiency area. In this paper, a frequency scalable publish-subscribe filter forwarding node has been proposed and implemented for addressing this challenge. The frequency scaling filter can operate on three different frequencies, which adapts its capacity and power on different network throughput. Our work...
It has been a decade since the National Institute of Standards and Technology (NIST) has selected the Rijndael algorithm as the Advanced Encryption Standard (AES). Since then, AES becomes the new block cipher standard of US government. A couple of years ago, with the shift of the technological trend towards the power aware system design, low power AES architectures gain importance over area and performance...
Auto white balancing is the process of keeping the color of objects constant automatically under different illumination conditions by calculating a number of parameters from the image data. These parameters are used to change the image pixel values to keep the color constant. This paper discusses the Lam's auto white balance algorithm and presents a novel, high-performance and cost-effective implementation...
Throughput is a key performance metric for streaming FFT architectures. However, increasing spatial parallelism to improve throughput introduces complex routing, thus resulting in high power consumption. In this paper, we propose a high throughput energy efficient parallel FFT architecture based on Cooley-Tukey algorithm. Multiple pipeline FFT processors using time-multiplexing are utilized to perform...
The need to integrate multiple wireless communication protocols into a single low-cost flexible hardware platform is prompted by the increasing number of emerging communication protocols and applications in modern embedded systems. The interleaving, one of the key components in the communication baseband, varies in differing communication protocols. A novel reconfigurable variable increment step (VIS)...
In this paper, we present an FPGA implementation of parallel-node low-density-parity-check convolution-code encoder and decoder. A 2.4 Gbit/s rate-1/2 (3, 6) LDPC convolutional-code encoder and decoder were implemented on an Alter a development and education board (DE4). Detailed power measurements of the FPGA board for various configurations of the design have been conducted to characterize the power...
Both Internet and semiconductor technology have advanced dramatically over the past decade. These advancements have made great impact on the conventional Internet infrastructure where networking equipment is dedicated on a per network basis. Router virtualization allows a single hardware router to serve packets from multiple networks while ensuring the same throughput and Quality of Service (QoS)...
Dynamically reconfigurable architectures, which can offer high performance, are increasingly used in different domains. High-speed reconfiguration process can be carried out by operating at high frequency but can also augment the power consumption. Thus the effort on increasing performance by accelerating the reconfiguration should take into account power consumption constraints. In this paper, we...
To implement the algorithms of information fusion in industry, the DSP-FPGA hybrid system is usually used which combined the advantage of DSP and FPGA, easy programming and handling custom interfaces, together. However, the hardware of the hybrid system is relatively complex. In this paper, a new platform, which supports multiple inputs of sensors solely on FPGA, has been put forward. With the state-of-art...
This paper presents an asynchronous FPGA that combines four-phase dual-rail encoding and LEDR (Level-Encoded Dual-Rail) encoding. Four-phase dual-rail encoding is used for small area and low power of function units, while LEDR encoding for high throughput and low power of data transfer. The proposed FPGA is fabricated in the e-Shuttle 65nm CMOS process and operates at 870 MHz. Compared to the synchronous...
In this work, our aim is to achieve a high throughput compact AES S-box with minimal power consumption. In most VLSI implementations, there exist a definite trade off between hardware performance and its operating requirements. In this work, we propose a novel pipelining arrangement over the compact composite field AES S-box such that both high throughput and low power are optimized. Our S-box outperformed...
Historically, computationally-intensive data processing for space-borne instruments has heavily relied on ground-based computing resources. But with recent advances in functional densities of Field-Programmable Gate-Arrays (FPGAs), there has been an increasing desire to shift more processing on-board; therefore relaxing the downlink data bandwidth requirements. Fast Fourier Transforms (FFTs) are commonly-used...
The objective of the SHA-3 NIST competition is to select, from multiple competing candidates, a standard algorithm for cryptographic hashing. The selected winner must have adequate cryptographic properties and good implementation characteristics over a wide range of target platforms, including both software and hardware. Performance evaluation in hardware is particularly challenging because of the...
Per-flow queuing is believed to be an effective approach to guarantee Quality of Service (QoS) in high performance routers. However, its brute-force implementation consumes a huge amount of memory and is not scalable as the number of flows increases. Dynamic Queue Sharing (DQS) mechanism, in which a physical queue is dynamically created on-demand when a new flow comes and released when the flow temporarily...
Square root is one of the fundamental arithmetic operations in signal and image processing algorithms. This article presents a novel pipelined architecture to implement N-bits fixed point square root in FPGA using non-restoring algorithm. Pipelining hazards were avoided by modifying the non-restoring algorithm resulting in a 30% improved latency time. Furthermore, the proposed architecture is flexible...
We provide a power analysis of a parallel implementation of the Cell Average Constant False Alarm Rate (CA-CFAR) algorithm in reconfigurable hardware, originally proposed by the authors. The design is based on a parallel processing scheme employing extensive data reuse and synchronized sliding windows over the input data sequence. A scalable parallel structure is designed and mapped on Xilinx Virtex...
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