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A new power estimation approach based on the decomposition of a digital system into basic operators is presented. This approach aims to estimate the energy consumption at early design phases of digital blocks implemented on FPGAs. Each operator has its own model which estimates the switching activity and the power consumption. By interconnecting several operators, statistical information is then propagated...
This paper describes a new methodology of construction of the internal activity block of an ICEM-CE model of an FPGA based on a predictive approach using the estimation tools of the dynamic power and the static timing proposed by the manufacturer of the integrated circuit.
As the availability of field-programmable gate arrays (FPGAs) increases, the importance of their power management has become crucial. For an efficient power management scheme, an accurate power estimation is required. The power consumption of FPGAs differs depending on the input, and previous power estimation methods have limitations which make it difficult to predict the input patterns which affect...
In this paper, a power analysis of a Nios II processor system is carried out. The methodology of power analysis includes SoPC (System on a Programmable Chip) system integration, architecture design compilation, software program compilation using a toolchain, system simulation and power analysis. In this work, a peak detection algorithm is implemented into the embedded processor system for power analysis...
Mobile networks and user equipments continuously evolve to circumvent the data traffic growth and the increasing number of users. However, the complexity and heterogeneity of such systems (3G, LTE, LTE-A, etc.) makes power one of the most critical metric. In this context, power estimation has become an unavoidable task in the design process. In this paper, a dynamic power estimation methodology for...
This paper presents an FPGA accelerated power estimation methodology for a Cadence Tensilica Xtensa LX5 ASIP. Based on hybrid functional level (FLPA) and instruction level power analysis (ILPA), the model can be mapped onto an FPGA together with the functional emulation. This enables fast and accurate estimation of application-specific power consumption and energy per task at early design stages which...
This paper investigates the possibility of creating an energy profile of a RISC processor instruction set in the prototyping phase, using FPGA implementation and physical measurements. In order to determine the power consumption at instruction-level, several programs have been developed and run on the processor implementation on FPGA. The experiments have focused at the following groups of instructions:...
Heterogeneous computing is gaining attention from both industry and academia nowadays. One driving factor for heterogeneous computing is the power efficiency. GPU and FPGA have been reported to achieve much higher power efficiency over CPU on many applications. Comparisons between GPU and FPGA show different characteristics of GPU and FPGA in accelerated computing. Some tasks run better on GPU, some...
This paper presents the application of an accurate power estimation model for design-stage processors that can be mapped onto an FPGA together with the functional emulation. Based on a hybrid functional level power analysis (FLPA) and instruction level power analysis (ILPA) approach, the model enables the estimation of application-specific power consumption and energy per task at very early design...
Power consumption in programmable devices has become a primary factor in design flow. Among the main concerns of power consumption, application performance, battery life, thermal challenges, or reliability, power consumption is crucial in FPGA designs for powered battery equipment. In this paper, we study the FPGA-based design for Sobel Edge Detection algorithm for low cost fall detector and we present...
FPGA is considered to be a good platform for rapid prototyping of embedded designs. The power consumption is a growing problem with FPGAs, which is required to be optimized. In this paper, a method is proposed to estimate the dynamic power consumption of Micro Blaze based processing unit used in embedded designs for FPGA. The proposed method is based on experimental bench of implemented designs where...
There is 67.04% dynamic power reduction with LVCMOS12 when we migrate from 90-nm Spartan-3 FPGA to 40-nm Virtex-6 FPGA. There is 81.19%, 92.05% dynamic power reduction when using LVCMOS12 in place of HSTL_II_18 and SSTL2_I_DCI respectively. We achieved 65.56%, 72.59% and 73.41% dynamic power reduction in ALU with LVDCI IO standard in place of LVDCI_DV2, HSTL_I, and LVCMOS12 respectively. There is...
Power becomes an ever-increasing concern due to the growing design complexity and the shrinking process technology. Power estimation at an early stage of electronic design automation (EDA) flow is essential in order to handle the design issues much earlier. Also power due to the routing resources is a dominant in field-programmable gate arrays (FPGAs). In this paper, we introduce a methodology for...
This paper proposes an efficient Hybrid System Level (HSL) power estimation methodology for MPSoC. Within this methodology, the Functional Level Power Analysis (FLPA) is extended to set up generic power models for the different parts of the system. Then, a simulation framework is developed at the transactional level to evaluate accurately the activities used in the related power models. The combination...
This paper proposes an efficient Hybrid System Level (HSL) power estimation methodology for FPGA-based MPSoC. Within this methodology, the Functional Level Power Analysis (FLPA) is extended to set up generic power models for the different parts of the system. Then, a simulation framework is developed at the transactional level to evaluate accurately the activities used in the related power models...
In high frequency FPGAs with technology scale shrinking and threshold voltage value decreasing and based on existing large numbers of unused resources, leakage power has a considerable contribution in total power consumption. On the other hand, process variation, as an important challenge in nano-scale technologies, has a great impact on leakage power of FPGAs. Reconfigurability of FPGAs makes an...
Motion Estimation (ME) is the most computationally intensive and most power consuming part of video compression and video enhancement systems. In this paper, we propose a novel dynamic power estimation technique for ME hardware. We estimated the power consumption of a full search ME hardware implementation on a Xilinx Virtex II FPGA using several existing high and low level dynamic power estimation...
Leakage power in nano-scale technologies is an important source of power consumption. Moreover, FP-GAs with low utilization rates consume large leakage power in their routing and logical resources. As FPGA routing architecture incorporates large number of transistors, leakage power of routing resources contributes the majority of total leakage power consumption. In this paper, a pre-routing prediction...
Nowadays, System-on-Chip architectures are composed of several execution resources which support complex applications. These applications increasingly need flexibility to adapt to their environment. Embed a reconfigurable resource in these SoC enables to flexibilize the hardware by sharing silicon area and limiting the cost of the global circuit. Partial reconfiguration is more and more used since...
This paper presents experimental measurements of power consumption for core logic of a 65-nm Cyclone III FPGA and its comparison with the value predicted by the power estimation tool. The laboratory work is described, including the measurement setup, the benchmark circuits, and the CAD flows utilized to obtain power estimations. The selected circuits used as benchmarks were different type of multipliers...
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