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This paper describes a new methodology of construction of the internal activity block of an ICEM-CE model of an FPGA based on a predictive approach using the estimation tools of the dynamic power and the static timing proposed by the manufacturer of the integrated circuit.
The recent rise of image processing circuits all along with the persistent quest for higher levels of performance have enormously contributed to the need of creating more efficient types of image processing circuit. For that, we have proposed a new design that offers us not only a less consuming circuit but also a faster one. Our new design has been tested and has given an interesting gain in power...
The main aim of this work is to study and show power reduction by using clock gating techniques with pulse enable concept. In this two 8 bit input data and a MUX 4:1 for selection of instruction which is a combination of logic and arithmetic operation's and total of 11 instruction are performed in the proposed design. This technique is applied on the D Flip-Flop based gated clock ALU & negative...
In this paper 64-bit energy efficient Arithmetic Logic Unit (ALU) is designed in verilog with the help of clock gating technique. We can reduce dynamic power and dynamic current of 64-bit ALU by using clock gating technique. This design is implemented on XC6VLX75T device, −3 speed grade and Virtex-6 FPGA. When clock logic is applied to target device, we are achieving 67.74% and 65.84% less reduction...
In this work, Virtex-6 is Target 40nm FPGA Device. Xilinx ISE 14.1 is an ISE Design tool. RAM is a target design. Clock Gating is a technique which decreases clock power but increases Logic Power due to added Logic in Design. Irrespective of increase in number of Signal and IO buffer due to Clock Gating, there is significant decrease in IO Power and Dynamic Power due to decrease in number of frequency...
There is 67.04% dynamic power reduction with LVCMOS12 when we migrate from 90-nm Spartan-3 FPGA to 40-nm Virtex-6 FPGA. There is 81.19%, 92.05% dynamic power reduction when using LVCMOS12 in place of HSTL_II_18 and SSTL2_I_DCI respectively. We achieved 65.56%, 72.59% and 73.41% dynamic power reduction in ALU with LVDCI IO standard in place of LVDCI_DV2, HSTL_I, and LVCMOS12 respectively. There is...
In this paper, latch free clock gating techniques is applied in ALU to reduce clock power and dynamic power consumption of ALU. Clock power is 50%, 41.46%, 51.30%, 55.15% and 55.78% of total dynamic power when device operating frequency is 100MHz, 1GHz, 10GHz, 100GHz and 1 THz. After implementation of clock gating techniques in ALU, Clock power reduces to 17.85%, 23.39%, 26.49% and 27.19% of total...
This paper presented the analysis of total power dissipation of AP-DCD algorithm using field programmable gate arrays (FPGAs). The static and dynamic power dissipation investigated using leakage current, supply voltage, effective capacitance and toggling frequency of the AP-DCD algorithm. It was found that the effective capacitance of AP-DCD algorithm was the main factor for the dynamic power dissipation...
In this paper, we present a generalized network flow based algorithm for power-aware FPGA memory mapping. Our algorithm not only maps user-defined logical memories to physical embedded memory blocks under the memory resource constraint but also achieves minimum power consumption. The experimental results show that our algorithm was always able to efficiently generate optimal solutions for all test...
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