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The era of internet of things (IoT) envisions a world where electronics is integrated with our environment. This can be achieved with ubiquitous low power sensing devices. It is challenging to achieve low power computing in the IoT paradigm since most applications are data-centric. However, typical applications have low duty cycle processing where idle times can be exploited for energy savings. This...
This paper presents a power-efficient 10-bit SAR ADC. A novel comparator topology with a dynamic common-gate stage is proposed to increase the pre-amplification gain under a low power supply voltage, thereby reducing noise and offset. Statistical estimation and loading switching techniques are synergically combined to further improve the energy efficiency. Moreover, the SAR sequencer and clock generator...
This paper examines the problem of generating testing actions for electronic industry test systems designed for verification of electronic packages of UHF band. This paper shows complex problems of setting amplitude and time parameters of multichannel generators of test signals. The problems of multichannel wide range signal generation and frequency control, rise and fall time control, pulse time...
Driver circuits for small LCD (Liquid Crystal Display) are formed on the same glass substrate as LCD by means of TFTs (Thin Film Transistors), which is called SoG (System on Glass) technology. If the driver circuit is designed by nMOS transistor only, then production cost is reduced, because the pMOS process can be eliminated. In this paper, we propose a new nMOS 2-phase clock dynamic logic shift...
Adiabatic logic is an alternative architecture design style to reduce the power consumption of digital cores by using AC power supply instead of DC ones. The energy saving of the digital gates is strongly related to the efficiency of adiabatic AC power supplies. In this paper, we propose a resonant reversible power-clock supply design with four different phases. The resonance deviation between the...
In this paper a 12bit 10GSps current-steering digital-to-analog converter (DAC) in 280GHz fT 0.7um InP HBT technology is presented. The DAC core works in a double-sampling way, which reduces the maximum clock frequency by half. The double-sampling switch is separated to reduce the inter-symbol-interference. An improved current steer switch architecture is adopted to enhance high frequency dynamic...
This paper shows the relationship between switching/sampling frequency, samples number and sine wave fundamental frequency with the intention of giving a basis to understand how the algorithm was designed. It also punctuates mathematical and implementation constraints considered in the optimization algorithm design. Similarly it explains the numerical methods and procedures used in the algorithm to...
In this paper, a non-overlap clock (NVC) generator for high accuracy fully differential Switched Capacitor (SC) readout circuit which is applied in Micro-Electro Mechanical System (MEMS) differential sensor is proposed. Compared with traditional generator, generating a set of non-overlap clock, this circuit generates a new set of clocks which are being nested inside the primary non-overlap clocks,...
The clock synchronization technologies applied to controlling layer and primary equipment like intelligent switchgear of processing layer in intelligent substation are analyzed in this paper. IEEE1588 message timing mode, which can be accurate to nanosecond, is used as the mode of substation system, in order to fulfill the real-time and accuracy requirements of intelligent switchgears and remote control...
This paper presents a clock-feedthrough compensation technique for bootstrapped switches. The proposed technique utilizes a dummy transistor to generate a reverse voltage, which compensates the input-dependent error caused by clock feedthrough effect of sampling switch. Simulation result shows the differential sampling error of bootstrapped switch reduces from 7.2mV to 1.4mV for the worst case, operating...
Excessive IR-drop during scan shift can cause localized IR-drop around clock buffers and introduce dynamic clock skew. Excessive clock skew at neighboring scan flip-flops results in hold or setup timing violations corrupting test stimuli or test responses during shifting. We introduce a new method to assess the risk of such test data corruption at each scan cycle and flip-flop. The most likely cases...
Scan shift power consumption is one of the major concerns in low power circuits. While there are multiple design for testability (DFT) techniques proposed in the literature for addressing both peak and average shift power optimization, most of the solutions impose additional design overhead which may impact functional performance of the device. In this paper, we propose a novel frequency scaled segmented...
In the process of China's automated production, the upgrading and networking of old infrastructures becomes one of the key issues. With large quantity, numerous varieties and wide distribution, these infrastructures brings complex design work and high cost to network them into fieldbus, which greatly hamper the building of intelligent factories. This paper proposed an industrial-control solution to...
A novel concept instrumentation amplifier (IA) using an analog signal compression technique is suggested to achieve a large dynamic input range. A large analog input signal is segmented into a smaller analog signal to prevent saturating the analog output signal in the input stage of the IA. At the input stage, we apply a reference bias at a node between an input capacitor and an input MOS to function...
As fault-tolerant Networks-on-Chip (NoCs) become prevalent in reliable systems, their overhead must be accurately evaluated. In this paper, we evaluate the overhead of a soft error resilient real-time NoC router for ASICs in terms of area and power. We employ a power analysis framework and load profiles that provide accurate power figures. Furthermore, we analyze the power behavior in normal operation...
Reference drivers for charge-redistribution SAR ADCs require significant area and/or power. In this work, a low-power and area-efficient passive reference-voltage driving scheme for charge-redistribution SAR ADCs is proposed. An on-chip decoupling capacitor is pre-charged to a reference voltage during tracking phase and utilized to drive the DAC passively during conversion. The reference-voltage drops...
A compact differential voltage reference cell, which combines an original switched capacitor integrator with a digitally programmable bandgap core, is presented. The two-stage integrator maintains an always-valid output voltage while performing correlated double sampling to effectively reduce the effects of offset and flicker noise. Measurements performed on a prototype designed with the UMC 0.18...
This work presents a System-on-Chip designed for Energy-Harvested applications. It embeds an ARM® Cortex®-M0+ microcontroller, 4KB RAM, 4KB ROM, an ultra-low power frequency synthesizer, a custom power switch, and a Power Management Unit enabling Active and Sleep modes. The system fabricated in 28 nm FD-SOI technology achieves 2.7pJ/cycle at 16 MHz during active mode, and the core consumes 4.3 nW...
This paper presents a time-interleaved pipelined-SAR converter targeting a multi-band mobile communication receiver. The input buffer is based on a super-source follower and linearized by selecting a specific bias current and drain bias resistor. Time interleaved sampling time mismatch is resolved by using a common sample and hold circuit, and gain mismatch is corrected by fine tuning respective subADC...
A novel calibration technique and its all-digital implementation for the open-loop delay line is presented. Fully autonomous approach iteratively compares each digitally-controlled delay stage of the line with an on-chip reference delay, correspondingly tuning selected stage and memorizing associated settings. After correcting all individual stages, the total delay of the line is compared with the...
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