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This paper presents an AC-powered, boost-converter-based multi-segmented LED driver that maintains a high-power factor (PF) and accurate input current level, using a novel look-up table (LUT)-based digital control with background calibration and optimal switching mode selection schemes. The presented multi-segmented LED driver aims to reduce the costs of high-voltage capacitors and high-inductance...
This paper describes a novel readout integrated circuit (ROIC) for a nanoscale photoresistive image sensor array with a novel dual element readout and calibration method. The dual element readout increases detector signal sensitivity and sensor dynamic range. It works on the assumption that adjacent nanoscale detectors have similar illumination levels. A novel on-chip two-point calibration method...
In this paper, a 9-bit 1.3 GS/s single channel SAR ADC is presented. In conventional SAR ADCs, the capacitive DAC size grows exponentially with respect to converter resolution. This results in both signal bandwidth and conversion speed reduction. The proposed architecture implements binary search through a redundant capacitive DAC for the 5 first MSBs and through programmable comparator thresholds...
This paper introduces an architecture and design for high resolution, high linearity Nyquist rate SAR ADCs requiring only a single simple calibration at startup. The proposed architecture benefits from an intrinsically linear 1.5 bit ΣΔ DAC to resolve the fine bits of the SAR ADC after a coarse conversion phase with a monotonically switched capacitive DAC. The ΣΔ DAC is also used for a single shot...
The paper presents the description and analysis of a phenomenon, relating with successive approximation ADCs dynamic performance degradation due to the influence of impedance of the circuit that connects the reference source with the switched capacitors' common bus. The paper provides a detailed analysis of this phenomenon and demonstrates methods to mitigate its impact on the performance on switched-capacitor...
Wireless-powered chips are used in a wide range of applications, including biomedical implants. However, the resonant frequency of the power receiving circuit can be affected not only by process variations, but also by the changing environment. In order to optimize the power transfer and allow the chip to work despite these variations, a fully integrated tuning system is proposed. After having assessed...
This paper presents a new circuit technique named as “residue oversampling,” which is suitable for high-resolution analog-to-digital converters (ADCs). By adopting this technique and simplifying dynamic element matching (DEM), the impacts of capacitor mismatch and noise upon the successive-approximation register (SAR) ADCs are diminished significantly without calibrations. The proof-of-concept prototype...
This paper introduces an analog bandwidth mismatch compensation technique for Time-Interleaved Analog-to-Digital Converters (TI-ADCs). It takes advantage of a Fully Depleted Silicon On Insulator (FD-SOI) technology to compensate for the bandwidth mismatch errors among channels. Our technique utilizes the body-effect to adjust the on-resistance of the sampling switch, by means of a 6-bit Digital-to-Analog-Converter...
A single-channel lb/cycle 8-bit 400-MS/s successive-approximation register (SAR) analog-to-digital converter (ADC) is presented in this paper. The operation speed is enhanced by using the loop-unrolled technique in the coarse conversions. Moreover, we propose a timing control scheme which would shorten the critical timing path to alleviate the speed limitation in the fine conversions. Also, we propose...
Aiming at the application of neural signal detection system, this paper designs a 12-bit 200KS/s high resolution successive approximation analog-to-digital converter (SAR ADC) fabricated in SMIC 0.18-μm process. An optimized digital self-calibration technique is proposed to correct the static offset of the comparator and the mismatch of the capacitor array by using a correction capacitor array, achieving...
A 10bit 40MS/s asynchronous timing logic successive approximation analog-to-digital converter (SAR ADC) is presented, including a bootstrapped switch, a charge redistribution digital-to-analog converter(DAC) and a dynamic comparator. A redundancy compensation and a mismatch calibration are introduced to achieve conversion accuracy improvement. A monotonic capacitor switching technique is adopted to...
In high-speed pipeline or pipelined-SAR ADCs, conventional opamp-based residue amplifiers consume significant amounts of power due to stringent settling speed and accuracy requirements. A recent alternative approach employs a dynamic amplifier [1] to achieve a more efficient form of settling, stemming from the fact that slewing is more power efficient than exponential settling (Fig. 28.4.1). For example,...
Wireless communication systems and Ethernet networks call for moderate-resolution GS/s energy-efficient ADCs. While previous work [1] shows that the multi-bit per cycle SAR ADC can achieve low power due to various hardware reduction techniques, there are still a few limitations that restrain this architecture. First, the pre-charge slows down the logic and the DAC settling, especially during the MSB...
In recent years, the need for high performance RF sampling ADCs has driven impressive developments of pipelined-SAR and pipelined ADCs, all supported by time-interleaving [1–4]. All these designs use a closed loop MDAC amplifier in the first stage and digital calibration/equalization to alleviate finite gain, settling and memory effects, but the closed-loop amplifier remains a scaling bottleneck....
This paper presents a calibration scheme for reference error caused by signal dependent switching transient in a high speed SAR ADC. The scheme has a little hardware overhead, which is not dependent on the type of the input signal and is able to run in the background without interrupting the ADC's normal operation. The calibration along with the SAR ADC are implemented in a 65 nm CMOS and the measurement...
We present two versions of 12-bit 40MSPS SAR ADCs using a search algorithm so called generalized redundant. It offers the flexibility to relax the requirements on the DAC settling time. Two more bits of redundancy are included to allow a digital calibration based on a code density analysis to compensate the capacitors mismatching effects. A new monotonic switching algorithm is used for these prototypes,...
A divide-and-conquer approach to address comparator offset mismatch in loop-unrolled SAR ADC is presented. Redundancy and coarse foreground calibration mitigate MSB comparators offset mismatches. A novel background calibration loop matches LSB comparators offsets to a reference comparator. The proposed scheme avoids a dedicated calibration cycle that would slow down conversion. Additionally, it ensures...
This paper presents a 10-bit high-speed two-stage SAR ADC. Each bit uses a dedicated comparator to store its output and generate an asynchronous clock for the next comparison. By doing this, the SAR logic delay and power are significantly reduced. A modified bidirectional single-side switching technique is used to optimize the comparator speed and offset by controlling the input common mode voltage...
Most of the high speed low power ADCs are interleaved using calibration which have some drawback like calibration time, the complexity associated with calibration algorithm and its circuit implementation. Therefore a single channel calibration-free 12-bit ADC sampling at 600MS/s in 28nm UTBB FDSOI is presented. Selected ADC architecture of mixing Pipelined stage and Asynchronous SAR demonstrates advantages...
This paper presents a low-voltage and power-efficient 10-bit successive-approximation register (SAR) analog-to-digital converter (ADC). An input-range-adaptive (IRA) switching method is proposed to reduce the average switching power of capacitive-DAC (CDAC). By utilizing the comparator as a voltage-to-time converter (VTC) and implementation of time-domain quantizer, the input range is detected to...
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