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A 13-bit 160MS/s hybrid ADC in 65 nm CMOS is presented in this paper. By combining the pipelined, flash and SAR architectures, a hybrid ADC architecture is proposed to improve the power efficiency. An input offset storage technique of dynamic comparator is proposed to increase the conversion linearity. A reference voltage buffer with the charge compensation is proposed to save power and reduce the...
In this paper, the Smoluchoski effect will be explained and is further used to understand the physics of the current-voltage (I–V) characteristics of high-k MIM capacitors in mixed-signal CMOS technology application.
An improved active-quenching circuit and a linear counting circuit used for a silicon single photon avalanche diode (SPAD) are presented in this paper. The proposed quenching circuit is fast and compact. The linear counting circuit can achieve 10 bit large count range with a small capacitor, which can effectively reduce the area of pixel. Due to the significant advantages of low-cost, compactness...
This paper presents a parallel readout circuit for high density single photon avalanche diode (SPAD) pixel array. Each pixel consists of analog quenching circuit and counting circuit. Column parallel readout method is adopted and every eight columns of array pixel shares one multiplexer where the analog output signals of these pixels are selected to pass it subsequently. After that, the signals will...
Using active feedback technique an analogue four quadrant multiplier-divider presented in this paper has achieved a great dynamic range both at inputs and at the output, and a good linearity with nonlinearity error smaller than 2%. Moreever the circuit has a better independence from the manufacturing process and the geometrical size of MOS transistors.
The conversion time for high-speed analog-to-digital converters is limited by the rate at which the internal comparator(s) can amplify small voltages 1 into logic levels. Several comparators have been designed with response times of less than 10 ns [1,2]. However, these circuits are usually fabricated with bipolar transistors.
A 1.2 V, 10 b, 40 MS/s pipelined ADC fabricated in 0.13µm one-poly eight-metal (1P8M) standard CMOS process with MIM capacitors is presented. This ADC used a novel low-variation on-resistance CMOS sampling switch to improve the nonlinear effect and a two-stage recycling folded-cascode (RFC) amplifier with hybrid frequency compensation for power saving and low voltage supply requirements. By implementing...
In the frame of the design of a low noise amplifier for W-band applications, pads, inductors, and other circuit components such as capacitors, coplanar waveguides and interconnect lines have been custom designed in a 28 nm bulk CMOS technology and simulated by means of 3D electromagnetic (EM) simulator. In particular, this paper reports the design and test of stand-alone pads, capacitor and inductor...
The downscaling of the CMOS technology and the demand for low power impose new challenges on the design of mixed-mode integrated circuits, such as analog to digital converters. Consequently, the amplifier, which is one of the building blocks, has been the subject of extensive development. This paper presents recent advances in low-power technique options for the design of amplifiers within the context...
This paper presents a high-speed and high-gain dynamic residue amplifier for two-stage SAR-assisted pipeline ADC. Parametric amplification technique is incorporated in the residue amplifier to enhance the gain, in order to meet the industrial requirements of the residue amplifier of an ADC with ENOB ≥ 10.5 bits. From simulations the proposed circuit has shown a gain of 22.05 dB and a power consumption...
This paper presents a 124 to 184 GHz single-ended amplifier designed in 28-nm FDSOI CMOS technology. The amplifier consists of four common-source gain stages and broadband matching networks for input, output and inter-stage matching employing slow-wave shielded co-planar waveguides. Having a total power consumption of 31 mW, the amplifier achieves a peak gain of 10.1 dB at 167 GHz and a 3-dB bandwidth...
A zero-crossing based amplifier whose power is scalable to a sampling frequency is presented. An inverter-based zero-crossing detector (ZCD) is proposed to consume no static power consumption compared with a conventional ZCD using a class-A based preamplifier. A common-mode feedback (CMFB) circuit is adopted to calibrate a variation of a ZCD threshold voltage due to supply voltage and temperature...
In this paper, a 10b 100-to-500 kS/s asynchronous SAR ADC is proposed and prototyped in 0.18 μm CMOS. The supply voltage is scaled down appropriately for different sampling speeds to minimize the power consumption. At a 0.5-V supply voltage and a 100 kS/s sampling rate, the ADC achieves a signal-to-noise and distortion ratio of 56.35 dB and consumes 424 nW, resultin g in a figure of merit of 7.9 fJ/conversion-step...
This paper presents a generic model that links the compensation techniques used in two-stage amplifiers to the structures of three-stage amplifiers. Many previous designs can be derived from this model, and new three-stage amplifiers can potentially be constructed. A novel three-stage amplifier based on this generic model is proposed. Simulation results show that the proposed design outperforms many...
Analog-to-Digital Converts (ADC) are becoming essential to the function of ultra-high speed interconnects (IO) with complex modulation schemes, while at the same time reduction in supply voltage has negatively impacted the performance of such circuits. However the improvement in delay times and reduction in logic size has made time-based ADCs attractive. To accomplish this, a Voltage-to-Time Converter...
A comparator-based circuit that uses switched-capacitor charging replaces the op amp in the multiplying digital-to-analog converter (MDAC) of a low-voltage algorithmic ADC. MDAC output swing beyond Vdd allows greater than rail-to-rail ADC input range. At a supply voltage of 0.55 V, the ADC achieves 8.4 bit ENOB and 1.4 Vpp differential input range. It occupies 0.65 mm2 in 0.25-μm CMOS and dissipates...
Filter-banks based on a gm-C topology are popular in acoustic sensor systems targeting spectral analysis. Their benefits lie in a very low power consumption and center-frequency scalability through gm-tuning to cover the audio frequency range. However the linear signal swing at the output of the filter is limited due to the inherent non-linearity of the input transistors in a differential pair. This...
This paper presents 3D IC design of a fully integrated four-phase buck converter. The control circuit was implemented in the TSMC 0.18μm CMOS Mixed Signal RF General Purpose MiM Al 1P6M 1.8 & 3.3V process while the passive components were implemented in the tMt Glass Substrate Integrated Passive Device (IPD) Process, and then these two dies are stacked. Thus, a high output loading current can...
In this paper, an 8-channel area-efficient low-power current-mode analog front-end amplifier (AFEA) is designed for EEG signal recording. The AFEA is composed of eight capacitive coupled transconductors (CCGMs), current-mode band-pass filters (CMBPFs), and programmable current-gain amplifiers (PCGAs) with a multiplexer (MUX), a transimpedance amplifier (TIA), and an offset current cancellation loop...
In this paper, a small-signal analysis of two SOI CMOS digitally tunable capacitor architectures intended for RF antenna tuning is provided. A mathematical model is derived and used to compare both architectures in terms of quality factor (Q-factor). The architecture with better Q-factor has been selected for implementation in a 130 nm SOI CMOS technology. To evaluate its potential for antenna aperture...
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