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A 16-core voltage-stacked IC integrated with a switched-capacitor DC-DC converter demonstrates efficient power delivery. To overcome inter-layer voltage noise issues, the test chip implements and evaluates the benefits of self-timed clocking and clock-phase interleaving. The integrated converter offers minimum voltage guarantees and further reduces voltage noise.
A low power CMOS latched comparator has been designed in TSMC 0.18um employ neutralization technique for reducing Kickback Noise. The simulation results demonstrate that it can work at 1GHz suitable for high speed applications. Measurement results prove that the latched comparator consumes 246uW with a power supply of 1.2v at 10MHz. A simulation method for accurately determining dynamic offset in...
A digitally trimmable voltage reference is proposed, achieving a tight distribution of temperature coefficient and output voltage, along with pA-range current consumption for Vdd=0.5-3.0V. Using 2 temperature point digital trimming, the temperature coefficient and nominal output voltage are within 5.3-47.4ppm/°C and 175.2-176.5mV across 25 dies in 0.13μm CMOS. Non-trimmable versions are also implemented...
An on-chip buck converter with 3D chip stacking is proposed and the operation is experimentally verified. The manufactured converter achieves a maximum power efficiency of 62% for an output current of 70mA with a switching frequency of 200MHz and a 2x2mm on-chip LC output filter in 0.35mum CMOS. The use of glass epoxy interposer to increase the maximum power efficiency up to 71.3%, and the power efficiency...
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