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Dynamically reconfigurable computing devices have the ability to adapt their hardware to application demands, providing the performance of hardware acceleration, as well as high flexibility, at competitive costs. For these reasons, FPGA-based reconfigurable systems are becoming popular in many application domains, including soft real-time computing. Unfortunately, one of their biggest limitations...
Modern multi-processor systems-on-a-chip currently count on computational resources previously only seen on general purpose machines. Each more, the evolution on the manufacturing process allows more features to be included on these embedded systems and determine an increased complexity of their hardware and software design. This increase of design complexity requires tools that may reduce the time...
System response time is a key element in hard real time systems. In classical Real Time Operating Systems (RTOS) based on software schedulers, overhead and jitter are a major problem when the number of tasks and the rate of context switches are high. Increased values for those parameters over admissible values can lead to performance degradation, increased power consumption or even deadline misses...
In multitasking real-time systems, the WCET of each task and also the effects of interferences between tasks in the worst-case scenario need to be calculated. This is especially complex with data caches. In this paper, we propose a small instruction-driven data cache (256 bytes) that effectively exploits locality. It works by preselecting a subset of memory instructions that will have data cache replacement...
Cyber Physical Systems are composed of many embedded systems which monitor and control the physical processes for tight integrations of computation and physical processes. Such embedded systems require not only real-time capabilities but also high throughput and low power consumption. High throughput is mainly achieved by parallel architectures such as Simultaneous Multithreading (SMT) and Chip Multiprocessor...
Transactional Memory (TM) has been touted as one of the most promising approaches to concurrent programming for multi-core processors. By combining ease of use with high scalability potential, as well as checkpointing capabilities particularly useful for developing dependable software, TM has attracted considerable attention from the research community. Many of its facets have been studied over the...
This paper provides an overview of some principles and mechanisms to securely operate mixed-criticality real-time systems on embedded platforms. Those principles are illustrated with PharOS a complete set of tools to design, implement and execute real-time systems on automotive embedded platforms. The keystone of this approach is a dynamic time-triggered methodology that supports full temporal isolation...
This paper presents a run-time monitoring framework to detect end-to-end timing constraint violations of event flows in distributed real-time systems. The framework analyzes every event on possible event flow paths and automatically inserts timing fault checks for run-time detection. When the framework detects a timing violation, it provides users with the event flow's run-time path and the time consumption...
In a real-time context, designing the software relies on insuring deterministic behavior and predictability. With system controlling several sensors and actuators sampled at different rates the scheduling theory associates the notion of Hyperperiod. It is a major factor of complexity whether for scheduling validation (simulation), or for generation of the corresponding tables in the case of pure off-line...
Theoretical real-time research generally neglects context switch times. But in recent embedded applications which consist of dozens of threads with very short execution times, their impact is too serious to be ignored. We present a hard real-time scheduling algorithm that perfectly hides the context switch times of an arbitrary number of threads. It requires a Simultaneous Multithreaded (SMT) processor...
In multitasking real-time systems it is required to compute the WCET of each task and also the effects of interferences between tasks in the worst case. This is complex with variable latency hardware usually found in the fetch path of commercial processors. Some methods disable cache replacement so that it is easier to model the cache behavior. Lock-MS is an ILP based method to obtain the best selection...
Transactional memory is a promising, optimistic synchronization mechanism for chip-multiprocessor systems. The simplicity of atomic sections, instead of using explicit locks, is also appealing for real-time systems. In this paper an implementation of real-time transactional memory (RTTM) in the context of a real-time Java chip-multiprocessor (CMP) is presented. To provide a predictable and analyzable...
In a Micro-grid research platform by studying distributed generation with distributed power, the reliability and data real-time of Data Acquisition System, directly affect the validity and accuracy of Control System Operation. In the process of design Data acquisition system, we put forward the optimization communication model by the combination between completion port and the thread pool, the model...
Today, mobile and embedded real time systems have to cope with the migration and allocation of multiple software tasks running on top of a real time operating system (RTOS) residing on one or several processors. For scaling of each task set and processor configuration, instruction set simulation and worst case timing analysis are typically applied. This paper presents a complementary approach for...
The importance of accounting for interrupts in multiprocessor real-time schedulability analysis is discussed. Three interrupt accounting methods, two of which are newly described here, are analyzed and compared.
Timing correctness of hard real-time systems is guaranteed by schedulability analysis and worst-case execution time (WCET) analysis of programs. Traditional WCET analysis mainly deals with application programs and has achieved success in industry. Timing analysis of application programs along cannot guarantee correctness of complete systems consisting RTOS. WCET tools designed for application program...
In the context of large versatile platform for embedded real time system on chip, a fine grained dynamically reconfigurable architecture could be used as one possible computational resource. In order to manage efficiently this resource we need a specific OS kernel able to manage such a hardware adaptable architecture. Both the history of micro-processor based system and our previous work based on...
Load imbalance cause significant performance degradation in High Performance Computing applications. In our previous work we showed that load imbalance can be alleviated by modern MT processors that provide mechanisms for controlling the allocation of processors internal resources. In that work, we applied static, hand-tuned resource allocations to balance HPC applications, providing improvements...
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