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Modern semiconductor chips offer a FPGA, A Hard Microcontroller and a programmable Analog circuitry all integrated on a single chip, which gives the system designer a full featured, easy-to-use design and development platform where all the units are programmable and under full control of the designer, Combining this state of the art silicon chip with a Real Time Operating Systems (RTOS) gives an Engineer...
This paper proposes a new method for video enhancement based on context-based fusion technique with respect to surveillance applications in real-time. In addition, a FPGA-based design for the proposed method is also presented. The developed technique here outperforms the original methods by without complex formulas and being time-efficient, whereas the output videos still keep a high quality. The...
Multi-Context Runtime Reconfigurable FPGAs have unique characteristics that make them extremely vulnerable to Hardware Trojan (HT). These FPGA families reconfigure themselves every clock cycle updating the functionality of the data path. A State Transition Controller (STC) typically holds the configuration code for each of the contexts. This architecture makes these type of architectures very efficient,...
Recently, studies have matured of field programmable gate arrays (FPGAs) that realize hardware acceleration. For such hardware acceleration on FPGAs, hugely parallel computation is frequently used. Consequently, numerous identical circuits are implemented onto an FPGA. However, identical configuration contexts of numerous identical circuits are stored on different regions of the configuration memory...
Nowadays, FPGAs are integrated in high-performance computing systems, servers, or even used as accelerators in System-on-Chip (SoC) platforms. Since the execution is performed in hardware, FPGA gives much higher performance and lower energy consumption compared to most microprocessor-based systems. However, the room to improve FPGA performance still exists, e.g. when it is used by multiple users....
High Level Synthesis (HLS) tools improve the speed of FPGA hardware design entry compared to traditional hardware description languages by raising the level of design abstraction. Using compiler directives to guide the tool, a wide variety of hardware architectures can be obtained without modification of the original behavioural code. However, selecting an optimal application of directives from this...
This paper presents a fast systolic priority queue architecture usable in a traffic manager. The purpose of the traffic manager is to schedule the departure of packets on egress ports in a network processing unit. In the context of this work, this scheduling should ensure that packets are sent in such a way to meet the allowed bandwidth quotas for each packet flow. Also, an important goal is to reduce...
This paper discusses an implementation of runtime verification for embedded software running on a System-on-Programmable-Chip (SoPC) composed of a micro-controller and a FPGA. The goal is to verify at runtime that the execution of the software on the micro-controller conforms to a set of properties. To do so, a minimal instrumentation of the software is used to send events to a set of monitors implemented...
Recently, to realize autonomous functions resembling those of humans on space systems, higher-performance embedded systems than those of current space systems are necessary for use in long-distance space missions. Currently, a parallel-operation-oriented optically reconfigurable gate array (ORGA) has been under development. The ORGA can support a nanosecond-order high-speed reconfiguration and high-density...
Recently, high-speed space optical communication requires real-time hardware operation instead of slow software operation on a processor. For such purposes, field programmable gate arrays (FPGAs) are extremely useful. In such hardware accelerations, a software algorithm is frequently implemented onto an FPGA as a parallel operation. However, in such implementations, many regions of the configuration...
Implementing applications on Reconfigurable Computing Architectures (RCAs) is an important research topic because of their high potential to accelerate a wide range of functions. Nevertheless, configuring and programming RCAs is a long-standing challenge. In this paper, we propose a design methodology to map an algorithm on an FPGA preconfigured with a Coarse-Grained Reconfigurable Architecture (CGRA)...
The atan2 function computes the polar angle arctan(y/x) of a point given by its cartesian coordinates. It is widely used in digital signal processing to recover the phase of a signal. This article studies for this context the implementation of atan2 with fixed-point inputs and outputs. It compares the prevalent CORDIC shift-and-add algorithm to two multiplier-based techniques. The first one computes...
Existing SRAM-based Field Programmable Gate Arrays (FPGAs) are very sensitive to Single Event Effects (SEE) phenomena in harsh environments. To protect applications running on SRAM-based FPGAs from SEE, those applications mainly relay on resources redundancy approaches, which involve significant resources overhead. New proposed fault mitigation approaches use Partial Dynamic Reconfiguration to overcome...
With the prevalence of reconfigurable computing, many relevant courses are designed and taught to graduate students. Traditional Field Programmable Gate Arrays (FPGAs) based hardware platforms are far from satisfying to reflect the important criteria characterizing a general reconfigurable computing system. In order to provide students a comprehensive understanding of reconfigurable computing system...
The design and implementation of a multitasking runtime system for mixed-architecture applications on a tightly coupled FPGA-CPU platform is presented. The runtime environment and the user applications assume an underlying machine that encompasses multiple computing architectures within a unified machine model. Using this model, a unified process scheduling mechanism was developed that enables concurrent...
When partially reconfigurable, FPGA-based, systems allow to dynamically hot-plug processors, the number of possible software configurations increases and the dynamic sharing of hardware peripherals becomes problematic. Moreover, the debugging of application processes, which needs physical devices to communicate with remote users or debuggers, is a critical service that becomes extremely difficult...
Overheads due to context switching and external interrupt management are core characteristics for Real-Time Operating Systems (RTOS) since they play a central role in their performance and timeliness. In this paper we evaluate two core characteristics for the Real-Time Executive for Multiprocessor Systems (RTEMS), an operating system used for supporting space applications. Our assessment makes use...
Reconfigurable architectures have found use in a wide range of application domains, but mostly as static accelerators for computationally intensive functions. Commodity computing adoption has not taken off due primarily to design complexity challenges. Yet reconfigurable architectures offer significant advantages in terms of sharing hardware between distinct isolated tasks, under tight time constraints...
This paper presents a novel real-time hardware implementation of the ViBe (VIsual Background Extractor) background generation algorithm in reconfigurable FPGA device. This novel method combines the advantages of typical recursive and non-recursive approaches and achieves very good foreground object segmentation results. In this work the issue of porting ViBe to a FPGA hardware platform is discussed,...
Dynamically reconfigurable computing devices have the ability to adapt their hardware to application demands, providing the performance of hardware acceleration, as well as high flexibility, at competitive costs. For these reasons, FPGA-based reconfigurable systems are becoming popular in many application domains, including soft real-time computing. Unfortunately, one of their biggest limitations...
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