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The FSM-SADF model of computation is especially suitable for analysing real-time applications with input-dependent behaviour such as different modes, variable execution times and scalable parallelism. Although FSM-SADF specifies which scenario transitions are possible, it does not specify how and when they are decided at runtime. Multiple actors of a scenario, e.g. video stream header parsing, may...
Software-defined networking (SDN) renovates traditional networking systems by replacing a distributed, per-switch control plane with a (logically) centralized one. To design a scalable, highly available SDN control plane, it is inevitable to disseminate the network state to multiple instances horizontally by using measures like replication and partitioning. However, some recent studies reported that...
Data center networks widely uses TCP for communication between the servers as it provides reliability and congestion control. However, TCP does not work well for certain type of communication patterns. One such a pattern is barrier synchronized many to one communication. During this type of data transmissions, multiple servers simultaneously transmits data to a single client and also the client cannot...
Computation is increasingly moving to the data enter. Thus, the energy used by CPUs in the data centeris gaining importance. The centralization of computation in the data center has also led to much commonality between the applications running there. For example, there are many instances of similar or identical versions of the Apache web server running in a large data center. Many of these applications,...
In high bandwidth and low latency data center networks, when multiple data senders simultaneously communicate with a single receiver, namely in many-to-one communication pattern, it is frequently occurred that the burst data overload the receiver's switch buffers, which leads to TCP throughput collapse. This phenomenon is termed to TCP Incast problem, which has become a new hot research topic in recent...
Asynchronous NoC switch is proposed as a robust design to mitigate the impact of process variation. Asynchronous and synchronous network on chip design are implemented to evaluate the impact of process variation on the network throughput. Network on chip interconnects and clock distribution network are considered under process variation with the advance in technology. The variation in logic and interconnect...
Asynchronous NoC switch is proposed as a robust design to mitigate the impact of process variation. Circuit analysis is used to evaluate the influence of process variation on both synchronous and asynchronous designs. The delay and throughput variation are evaluated with different technologies. Although the asynchronous switch has large delay variation as compared to synchronous switch, high throughput...
Recently, there has been renewed interest in latency as a primary metric for mainstream data center applications. In this paper, we propose a coordinated mechanism for congestion control and multi-path transmission to reduce flow completion time in data centers. The approach leverages ECN to adaptively react to congestion, prioritizes flows according to their timeliness requirements, and evenly distributes...
Spectrum assigned by the Federal Communication Commission (FCC) for public safety has not been fully utilized. As such, communication service providers and equipment vendors desire to examine the feasibility of recouping their investment in spectrum purchase and management. We propose a cost-effective solution by introducing a cognitive extension that achieves desired frequency agility while utilizing...
Incast applications have grown in popularity with the advancement of data center technology. It is found that the TCP incast may suffer from the throughput collapse problem, as a consequence of TCP retransmission timeouts when the bottleneck buffer is overwhelmed and causes the packet losses. This is critical to the Quality of Service of cloud computing applications. While some previous literature...
In this work we propose a TCMS (Tightly Coupled Mesochronous Synchronizer)-based architecture of Globally-Asynchronous Locally-Synchronous (GALS) Network-on-Chips (NoC). The NoC is based on the GigaNoC approach, a scalable NoC featuring packet-switched wormhole routing. At a clock frequency of 750MHz a link bandwidth of up to 6 GByte/s is achieved. To provide a high computational performance, the...
TCP Incast, also known as TCP throughput collapse, is a term used to describe a link capacity under-utilization phenomenon in certain many-to-one communication patterns, typically in many datacenter applications. The main root cause of TCP Incast analyzed by prior works is attributed to packet drops at the congestion switch that result in TCP timeout. Congestion control algorithms have been developed...
Recent versions of the Java standard library offer flexible locking constructs that go beyond the language's built-in monitor locks in terms of features, and that can be fine-tuned to suit specific application scenarios. Under certain conditions, the use of these constructs can improve performance significantly, by reducing lock contention. However, the code transformations needed to convert between...
The reliability of a synchronizer depends on its recovery time from metastability, a time which is reduced if the delay through the synchronizer flip flops is large. The D to Q delay in a dual edge triggered D flip flop based on wagging is lower than in other designs allowing more time for metastability recovery. We also apply wagging to the synchronizer itself, reducing its delay even more when compared...
In this paper, a Johnson-encoded Reconfigurable Synchronous/Bi-Synchronous (RSBS) FIFO is proposed which can adapt its operation to either synchronous or bi-synchronous mode. The proposed FIFO which can be used to interface modules in Voltage/Frequency Islands (VFI) based Networks-on-chip, is capable of alleviating the excessive energy consumption and high performance overhead of the conventional...
One of the main challenges in the multi-core area is the communication and synchronization of the cores and the design of an efficient interconnection network that is scalable to multiple cores. In this paper we present an efficient implementation of a scalable system that is targeting multi-core systems. Each cluster node consists of 4 processors that support both explicit and implicit communication...
Customization of IP blocks in a multi-processor system-on-chip (MPSoC) is the historical approach to the cost-effective implementation of such systems. A recent trend consists of structuring a MPSoC into loosely coupled voltage and frequency islands to meet tight power budgets. In this context, synchronization between islands of synchronicity becomes a major design issue. Dual-clock FIFOs compare...
Network-on-chip architectures partitioned into several Voltage/Frequency Islands (VFIs) have been proposed to alleviate problems related to integration, excessive energy consumption and clock distribution. The architecture is composed of synchronous switches that communicate with each other using bi-synchronous FIFOs. However, these FIFOs are not needed if adjacent switches belong to the same clock...
In this paper, we propose a TDMA based multi-channel MAC protocol to improve the channel efficiency and network performance in wireless ad hoc networks. There are two main problems encountered in all related works in designing multi-channel MAC protocols. The first problem is the rendezvous problem and the second is multi-channel hidden node problem. In order to solve these problems, most of previous...
This paper proposes a RSU assisted multi-channel coordination MAC (RAMC) protocol that fully utilizes all DSRC channels to provide simultaneous safety and non-safety communications. Within the radio range of a roadside unit (RSU), vehicles are free to tune to any service channels. The RSU monitors all the safety messages being transmitted in both the control and service channels. Periodically, the...
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