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The cutoff frequencies and maximum frequencies of operation of short channel transistors have reached the terahertz (THz) range. In such devices, the ballistic electron transport, which was first proposed nearly 40 years ago, affects all the device characteristics - from the linear region (dominated by the so-called “ballistic mobility”) to a high field region affected by the ballistic injection....
A 16-bit (5+11) segmented digital-to-analog converter (DAC), based on a voltage mode R-2R topology that is able to derive high resolution and high performance, in terms of INL and DNL, and less area and power consumption comparing with conventional DACs. It is designed and simulated in 65nm CMOS process. A current compensating technique is used to achieve good dynamic performance. The 16 bit R-2R...
Operational amplifier is an important portion of various analog and mixed signal circuits. Today use of mixed mode integrated circuits rises. Analog circuits particularly operational amplifiers in CMOS technology are difficult to design due to challenging and time consuming tasks like counting various conflicting benchmarks and a wide variety of design factors. This paper presents the use of Particle...
This paper presents the performance analysis of single electron transistor(SET) low power Arithmetic & Logical selective Unit. SET which is low power device is used to produce new features, which is nearly impossible to achieve with only CMOS circuit. Efficient SET 4∶1 MUX is designed & verified as well as quaternary selective circuit is proposed. As well one bit full adder, AND, OR and XOR...
A flash fast-locking digital phase-locked loop (DPLL) is presented using transistor level 50 nm CMOS technology and 1V power supply in LT SPICE. The DPLL operation includes two stages: (1) a coarse-tuning stage for frequency tracking which employs a flash algorithm similar to the one employed in flash A/D converters (ADCs) and (2) a fine-tuning stage similar to conventional (classical) DPLLs. The...
We propose a new semi-empirical method for estimation of Single Event Upset (SEU) cross-section for SRAM Dual Interlocked Cells (DICE) with known distance between neighboring sensitive volumes. The method is based on experimental analysis of SEU maps in sub-100 nm 6T SRAM along with layout considerations and SPICE simulations. It could help to significantly improve SEE robustness of modern CMOS VLSI...
The paper deals with a simplified model of the HP TiO2 memristor, which can be used for identifying the parameters of built-in memristors, i.e. in cases where there is only a limited set of measurements possible. The memristor is excited by a rectangular voltage waveform and the built-in measuring device can measure the times when the memristor current crosses several thresholds. The proposed approach...
We present analytical expressions for MOSFET distortion as a function of inversion level, represented by gm/ID as a proxy. The expressions are particularly useful for moderate inversion, where the generic textbook equations fail. Unlike previous approaches, the method requires only a small number of technology parameters. For an estimation of gm nonlinearity, only the subthreshold slope is needed...
Memristor is a nano device that exhibits unique I-V pinched hysteresis loop with switching mechanism and has ability to remember its last state. These interesting memristor characteristics encourage researchers to understand the new device and develop its potential applications. The problem is memristor has not yet available in current market due to the cost and technical difficulties in fabrication...
This paper reports a memory resistance (memristor) behavior for low power integrated circuit applications. The power dissipation of memristor is analyzed by using Simulation Program with Integrated Circuit Emphasis (SPICE). For power dissipation checking, the memristor is driven by some power supplies: sinusoidal, trapezoidal, triangular, and rectangle waveforms. From the SPICE simulation results,...
In this work a comprehensive SPICE model is demonstrated for perimeter-gated single photon avalanche diodes (PGSPAD) fabricated in commercial 0.5 µm CMOS process. This model simulates the trigger of an avalanche event of PGSPAD due to photon absorption, along with the quenching behavior. It also simulates the I–V characteristic, where the breakdown voltage can be modulated with applied gate voltage...
An original analog function synthesizer circuit with increased accuracy will be presented, allowing to implement a multitude of important continuous mathematical functions. The accuracy of the proposed structure is excellent and the range of the input variable is strongly extended as a result of the third-order approximation of the implemented functions. The circuit performance is expected to be stable...
Estimating the failure probability of nano-scale generic logic cells is a key point for the evaluation of digital system reliability. Noise-induced input variations with process-induced threshold voltage variations affect the probability of correct operation of logic cells. This work quantitatively analyses the probability of invalid output of a cell by introducing novel analytical and semi-analytical...
In this study, a new voltage-mode multifunction filter based on single current operational amplifier (COA) is presented. The proposed topology employs single CMOS based COA and it provides lowpass, highpass, bandpass and notch filter functions by modifying only three admittances. The COA used in this study is implemented by CMOS based current conveyors and the validity of the proposed circuit is verified...
This paper presents a MOS current mode logic (MCML) square root carry select adder (SQ-CSA) which can be used as an alternative to MCML ripple carry adder (RCA) when the number of bits in the input words is large. The proposed 16-bit MCML SQ-CSA has been implemented and simulated in PSPICE using TSMC 180 nm CMOS technology parameters. Its performance has been compared with 16-bit RCAs based on CMOS...
This paper presents the design of a first-order close-loop VCO based ΔΣ ADC. Unlike other VCO based ADC, it does not contain operational amplifier which is power hungry and scaling unfriendly. Also, by using two VCOs referring to each other, it has an intrinsic DEM capability that improves SNDR degradation caused by mismatches in the feedback DAC. The design is low power and area efficient. A prototype...
In this paper, a CMOS monolithic light to sigma-delta modulator for environmental monitoring applications is newly proposed. The proposed chip is attractive due to the fact that analog processing circuits and light sensor are integrated robustly and compactly. The output signal of the proposed chip is a pulse stream, it could be easily sent over a wide range of transmission media, such as PSN, radio,...
In this paper, single operational transresistance amplifier (OTRA) based biquadratic filter configuration is proposed. The topology can be used to synthesize low pass, high pass and band pass filter functions with appropriate admittance choices. This configuration can implement filters with high quality factor which can be controlled independent of angular frequency. Workability of the proposed biquad...
Conductance variations in nanoelectronic resistive switches seriously affect the performance of hybrid CMOS/memristive circuits. In order to capture cycle-to-cycle variability by circuit simulation a standard model was extended for resistive switches based on the electrochemical metallization effect. The extension incorporates an additional process that simulates the randomness of the filament growth...
Planar fully-depleted SOI technology is becoming mainstream within STMicroelectronics, targeting modern mobile and consumer multimedia markets. This technology combines high performance and low power consumption, complemented by an excellent responsiveness to power management design techniques. The fabrication process is comparatively simple and is a low-risk evolutionary step from conventional planar...
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