The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Three-dimensional Field Programmable Gate Arrays (3D FPGAs) represent a viable alternative to overcome challenges of integration complexity in modern embedded systems. Mapping applications into 3D FPGAs requires a set of accompanying suite of Computer-Aided Design (CAD) tools. One of critical issue of a 3D FPGA-based implementation is the quality and efficiency of associated CAD algorithms. In this...
A major obstacle to the uptake of advanced fabrication nodes by small industry is high NRE costs, mainly due to initial mask generation. The Programmable Structured ASIC (psASIC) is intended to bridge the gap between FPGA and Structured ASIC approaches to application design. The psASIC prototype environment comprises a pair of stacked chips, one containing only logic and the other comprising only...
The authors explore and design the traditional field-programmable gate array (FPGA) interconnect topologies and architectures that can play an important role in improving performance and density. The main architectures under exploration are tree-based and island-style Manhattan Mesh. Mesh-based design is the most common industrial and academic architecture. Numerous research and industrial designs...
Among many challenges in the development of 3D-IC products, cost is one of the top concerns. Within cost elements, known-good-die (KGD) and 3D-IC integration yield, are among a few biggest impacting factors. In order to achieve high 3D-IC integration yield, build-in self-repairing, design-for-testing (DFT), diagnostic, and failure analysis (FA) capabilities, are very important elements of 3D-IC FPGA...
In this study, we propose a three-dimensional (3D) interconnect network implementation based on a modified Mesh-of-Clusters (MoC) topology for FPGA architecture design. Design and experimental setup is developed to demonstrate the improvement in performance, power and area of 2.5D and 3D MoC-based FPGA architecture. MoC starts with a mesh of nodes and builds a separate hierarchical network along each...
We describe the design and exploration methodology to optimize 3-dimensional (3D) heterogeneous interconnect fabric of Tree-based FPGA (HT-FPGA) by introducing a break-point at a particular tree level interconnect to optimize the speed, power consumption and area. The ability of the flow to decide a horizontal or vertical partitioning of the multilevel programmable tree network based on design specifications...
The CMOS technology scaling has greatly improved the overall performance and density of Field Programmable Gate Arrays (FPGAs). However, when looking at the performance metrics such as speed, area and power consumption, the gap is generally very wide for FPGAs compared to application specific integrated circuits (ASICs) mainly due to the programmable interconnect overhead. We propose a 3-dimensional...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.