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The paper presents the architectural domain analysis for FPGA (Field Programmable Gate Array) implementation of a polyphase filter bank channelizer with an embedded square root shaping filter in its polyphase engine that performs two different re-sampling tasks required for spectral shaping and for M-channel channelizer. In terms of algorithms; Radix-2 FFT, Prime Factor and Winograd Fourier Transform...
Implementing floating-point (FP) Fast Fourier Transforms (FFT) on Field Programmable Gate Arrays (FPGAs) still represents a challenging task. The limited resources on target devices coupled with the inherent complexity of the FFT are among factors limiting widespread utilization. This paper presents the design of a scalable, FP FFT core for synthesis on Xilinx FPGAs. Its architecture uses a radix-2...
This paper presents a modified pipeline single-path delay feedback (SDF) fast Fourier transform (FFT) architecture. The canonic signed digit (CSD) representation is used to design the function of complex multiplier, which is the main function block in the FFT processor. The processor of a 16-bit 16-point pipeline FFT is realized on the Xilinx Virtex-4 FPGAs. The achieved maximum clock frequency is...
A 2.048 GSPS fixed-point fixed-precision dynamic kernel function FFT processor with variable truncation scheme (VTS) is proposed and implemented for real-time wideband signal detection. Using Xilinx System Generator, single-signal detection is demonstrated for a bandwidth of 912 MHz with 16 MHz channelization and output throughput rates of 62.5 ns. The proposed design has an averaged single-signal...
In this paper, we proposed 2D FFT for 8times8 matrix without transpose of data by using multiple topology on 4times4 Torus. The proposed 2D FFT used parallel operation on 1D FFT and applied an effective calculation by executing a pipeline operation. We implement the proposed architecture on Xilinx Virtex-IV device and a detailed evaluation has been reported based on maximum system frequency, chip...
Efficient architectures for realizing MDCT/IMDCT are presented. Based on the symmetry property of trigonometric functions, N-point MDCT formula was transferred into an odd-even index paralleling process which can be achieved by two different types of decomposition, recursive formed DCT-II kernel or FFT-based DCT-IV kernel. Then a butterfly unit is employed to accelerate the computational speed. Furthermore,...
FFT algorithm is the popular software design for spectrum analyzer, but doesnpsilat work well for parallel hardware system due to complex calculation and huge memory requirement. Observing the key components of a spectrum analyzer are the intensities for respective frequencies, we propose a Goertzel algorithm to directly extract the intensity factors for respective frequency components in the input...
A new on-chip implementation of fast Fourier transform (FFT) based on Radix 2 is presented. The pipeline and parallel approaches are combined to introduce a new high speed FFT algorithm which increases resolution by using floating point calculations in its structures. The design has the merits of low complexity and high speed performance. Furthermore, latency reduction is an important issue to implement...
In this paper, we design and implement a 32-bit IEEE 754 single precision floating-point FFT processor. Usually, limited by long pipeline latency of floating-point operations and multi-port RAM access the throughput of FFT processors can only reach approximately one result per cycle. Through making some improvements on the design of butterfly unit and reorganization of the RAM access, almost a throughput...
Fast Fourier Transform (FFT) is the most basic and essential part of Software Defined Radio (SDR). Therefore, designing regular, reconfigurable, modular and low hardware complexity FFT computation block is very important. A single FFT block should be configurable for varying length FFT computation and also for computation of different transforms like DCT, DST etc. In this paper, the authors analyze...
In this paper, we propose a low multiplier and multiplication complexities 256-point fast Fourier transform (FFT) architecture, especially for WiMAX 802.16a systems. Based on the radix-16 FFT algorithm, the proposed FFT architecture utilizes cascaded simplified radix-24 single-path delay feedback (SDF) structures. The control circuit of the proposed simplified radix-24 SDF FFT architecture is simple...
A configurable floating-point coprocessor by a FPGA is designed to enhance the computational capability of the digital platform based on the fixed-point DSP, with which the platform will be competent to implement intensively computational tasks. Detailed design procedures of the coprocessor are presented. A new division algorithm is proposed by combining the lookup-table algorithm and multiplicative...
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